Type7CacheInformation.c 14 KB

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  1. /** @file
  2. SMBIOS Type 7 (Cache information) table for ARM RD platforms.
  3. This file installs SMBIOS Type 7 (Cache information) table for Arm's
  4. Reference Design platforms. It includes information about cache levels
  5. implemented, cache configuration, ways of associativity and other
  6. information related to cache memory installed.
  7. Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
  8. SPDX-License-Identifier: BSD-2-Clause-Patent
  9. @par Specification Reference:
  10. - SMBIOS Reference Specification 3.4.0, Chapter 7.8
  11. **/
  12. #include <Library/DebugLib.h>
  13. #include <Protocol/Smbios.h>
  14. #include "SgiPlatform.h"
  15. #include "SmbiosPlatformDxe.h"
  16. #define TYPE7_STRINGS \
  17. "L1 Instruction\0" /* L1I */ \
  18. "L1 Data\0" /* L1D */ \
  19. "L2\0" /* L2 */ \
  20. "L3\0" /* L3 */ \
  21. "SLC\0" /* L4 */
  22. typedef enum {
  23. L1Instruction = 1,
  24. L1Data,
  25. L2,
  26. L3,
  27. Slc,
  28. } TYPE7_STRING_ELEMENTS;
  29. /* SMBIOS Type7 structure */
  30. #pragma pack(1)
  31. typedef struct {
  32. SMBIOS_TABLE_TYPE7 Base;
  33. CHAR8 Strings[sizeof (TYPE7_STRINGS)];
  34. } ARM_RD_SMBIOS_TYPE7;
  35. #pragma pack()
  36. /* Cache information */
  37. STATIC ARM_RD_SMBIOS_TYPE7 mArmRdSmbiosType7[] = {
  38. { // Entry 0, L1 instruction cache
  39. {
  40. {
  41. // SMBIOS header
  42. EFI_SMBIOS_TYPE_CACHE_INFORMATION, // Type 7
  43. sizeof (SMBIOS_TABLE_TYPE7), // Length
  44. SMBIOS_HANDLE_L1I_CACHE, // Handle number
  45. },
  46. L1Instruction,
  47. (
  48. (1 << 8) | // Write-back
  49. (1 << 7) | // Cache enabled
  50. (1 << 3) | // Cache socketed
  51. 0x0 // Cache level 1
  52. ),
  53. 0xFFFF, // Uses Maximum cache size 2 field
  54. 0xFFFF, // Uses Installed cache size 2 field
  55. {0, 1}, // Supported SRAM type unknown
  56. {0, 1}, // Current SRAM type unknown
  57. 0, // Cache Speed Unknown
  58. 0x02, // Error correction type unknown
  59. 0x03, // Instruction cache
  60. 0, // Associativity, update dynamically
  61. 0, // Maximum cache size 2, update dynamically
  62. 0 // Installed cache size 2, update dynamically
  63. },
  64. // Text strings (unformatted area)
  65. TYPE7_STRINGS
  66. },
  67. { // Entry 1, L1 data cache
  68. {
  69. {
  70. // SMBIOS header
  71. EFI_SMBIOS_TYPE_CACHE_INFORMATION, // Type 7
  72. sizeof (SMBIOS_TABLE_TYPE7), // Length
  73. SMBIOS_HANDLE_L1D_CACHE, // Handle number
  74. },
  75. L1Data,
  76. (
  77. (1 << 8) | // Write-back
  78. (1 << 7) | // Cache enabled
  79. (1 << 3) | // Cache socketed
  80. 0x0 // Cache level 1
  81. ),
  82. 0xFFFF, // Uses Maximum cache size 2 field
  83. 0xFFFF, // Uses Installed cache size 2 field
  84. {0, 1}, // Supported SRAM type unknown
  85. {0, 1}, // Current SRAM type unknown
  86. 0, // Cache Speed Unknown
  87. 0x02, // Error correction type unknown
  88. 0x04, // Data cache
  89. 0, // Associativity, update dynamically
  90. 0, // Maximum cache size 2, update dynamically
  91. 0 // Installed cache size 2, update dynamically
  92. },
  93. // Text strings (unformatted area)
  94. TYPE7_STRINGS
  95. },
  96. { // Entry 2, L2 cache
  97. {
  98. {
  99. // SMBIOS header
  100. EFI_SMBIOS_TYPE_CACHE_INFORMATION, // Type 7
  101. sizeof (SMBIOS_TABLE_TYPE7), // Length
  102. SMBIOS_HANDLE_L2_CACHE, // Handle number
  103. },
  104. L2,
  105. (
  106. (1 << 8) | // Write-back
  107. (1 << 7) | // Cache enabled
  108. (1 << 3) | // Cache socketed
  109. 0x1 // Cache level 2
  110. ),
  111. 0xFFFF, // Uses Maximum cache size 2 field
  112. 0xFFFF, // Uses Installed cache size 2 field
  113. {0, 1}, // Supported SRAM type unknown
  114. {0, 1}, // Current SRAM type unknown
  115. 0, // Cache Speed Unknown
  116. 0x02, // Error correction type unknown
  117. 0x05, // Unified cache
  118. 0, // Associativity, update dynamically
  119. 0, // Maximum cache size 2, update dynamically
  120. 0 // Installed cache size 2, update dynamically
  121. },
  122. // Text strings (unformatted area)
  123. TYPE7_STRINGS
  124. },
  125. { // Entry 3, L3 cache
  126. {
  127. {
  128. // SMBIOS header
  129. EFI_SMBIOS_TYPE_CACHE_INFORMATION, // Type 7
  130. sizeof (SMBIOS_TABLE_TYPE7), // Length
  131. SMBIOS_HANDLE_L3_CACHE, // Handle number
  132. },
  133. L3,
  134. (
  135. (1 << 8) | // Write-back
  136. (1 << 7) | // Cache enabled
  137. (1 << 3) | // Cache socketed
  138. 0x2 // Cache level 3
  139. ),
  140. 0xFFFF, // Uses Maximum cache size 2 field
  141. 0xFFFF, // Uses Installed cache size 2 field
  142. {0, 1}, // Supported SRAM type unknown
  143. {0, 1}, // Current SRAM type unknown
  144. 0, // Cache Speed Unknown
  145. 0x02, // Error correction type unknown
  146. 0x05, // Unified cache
  147. 0, // Associativity, update dynamically
  148. 0, // Maximum cache size 2, update dynamically
  149. 0 // Installed cache size 2, update dynamically
  150. },
  151. // Text strings (unformatted area)
  152. TYPE7_STRINGS
  153. },
  154. { // Entry 4, SLC Cache
  155. {
  156. {
  157. // SMBIOS header
  158. EFI_SMBIOS_TYPE_CACHE_INFORMATION, // Type 7
  159. sizeof (SMBIOS_TABLE_TYPE7), // Length
  160. SMBIOS_HANDLE_L4_CACHE, // Handle number
  161. },
  162. Slc,
  163. (
  164. (1 << 8) | // Write-back
  165. (1 << 7) | // Cache enabled
  166. (1 << 3) | // Cache socketed
  167. 0x3 // Cache level 4
  168. ),
  169. 0xFFFF, // Uses Maximum cache size 2 field
  170. 0xFFFF, // Uses Installed cache size 2 field
  171. {0, 1}, // Supported SRAM type unknown
  172. {0, 1}, // Current SRAM type unknown
  173. 0, // Cache Speed Unknown
  174. 0x02, // Error correction type unknown
  175. 0x05, // Unified cache
  176. 0, // Associativity, update dynamically
  177. 0, // Maximum cache size 2, update dynamically
  178. 0 // Installed cache size 2, update dynamically
  179. },
  180. // Text strings (unformatted area)
  181. TYPE7_STRINGS
  182. }
  183. };
  184. /**
  185. Install SMBIOS Cache information Table
  186. Install the SMBIOS Cache information (type 7) table for Arm's Reference
  187. Design platforms.
  188. @param[in] Smbios SMBIOS protocol.
  189. @retval EFI_SUCCESS Record was added.
  190. @retval EFI_NOT_FOUND Unknown product id.
  191. @retval EFI_OUT_OF_RESOURCES Record was not added.
  192. @retval EFI_ALREADY_STARTED The SmbiosHandle passed is already in use.
  193. **/
  194. EFI_STATUS
  195. InstallType7CacheInformation (
  196. IN EFI_SMBIOS_PROTOCOL *Smbios
  197. )
  198. {
  199. EFI_STATUS Status;
  200. EFI_SMBIOS_HANDLE SmbiosHandle;
  201. UINT8 CacheIdx;
  202. /* Update the cache attributes based on the product */
  203. switch (SgiGetProductId ()) {
  204. case Sgi575:
  205. /* L1 instruction cache */
  206. mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64; // 64KB
  207. mArmRdSmbiosType7[0].Base.InstalledSize2 = 64; // 64KB
  208. mArmRdSmbiosType7[0].Base.Associativity = CacheAssociativity4Way;
  209. /* L1 data cache */
  210. mArmRdSmbiosType7[1].Base.MaximumCacheSize2 = 64; // 64KB
  211. mArmRdSmbiosType7[1].Base.InstalledSize2 = 64; // 64KB
  212. mArmRdSmbiosType7[1].Base.Associativity = CacheAssociativity16Way;
  213. /* L2 cache */
  214. mArmRdSmbiosType7[2].Base.MaximumCacheSize2 = 512; // 512KB
  215. mArmRdSmbiosType7[2].Base.InstalledSize2 = 512; // 512KB
  216. mArmRdSmbiosType7[2].Base.Associativity = CacheAssociativity8Way;
  217. /* L3 cache */
  218. mArmRdSmbiosType7[3].Base.MaximumCacheSize2 = 2048; // 2MB
  219. mArmRdSmbiosType7[3].Base.InstalledSize2 = 2048; // 2MB
  220. mArmRdSmbiosType7[3].Base.Associativity = CacheAssociativity16Way;
  221. break;
  222. case RdN1Edge:
  223. case RdN1EdgeX2:
  224. /* L1 instruction cache */
  225. mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64; // 64KB
  226. mArmRdSmbiosType7[0].Base.InstalledSize2 = 64; // 64KB
  227. mArmRdSmbiosType7[0].Base.Associativity = CacheAssociativity4Way;
  228. /* L1 data cache */
  229. mArmRdSmbiosType7[1].Base.MaximumCacheSize2 = 64; // 64KB
  230. mArmRdSmbiosType7[1].Base.InstalledSize2 = 64; // 64KB
  231. mArmRdSmbiosType7[1].Base.Associativity = CacheAssociativity4Way;
  232. /* L2 cache */
  233. mArmRdSmbiosType7[2].Base.MaximumCacheSize2 = 512; // 512KB
  234. mArmRdSmbiosType7[2].Base.InstalledSize2 = 512; // 512KB
  235. mArmRdSmbiosType7[2].Base.Associativity = CacheAssociativity8Way;
  236. /* L3 cache */
  237. mArmRdSmbiosType7[3].Base.MaximumCacheSize2 = 2048; // 2MB
  238. mArmRdSmbiosType7[3].Base.InstalledSize2 = 2048; // 2MB
  239. mArmRdSmbiosType7[3].Base.Associativity = CacheAssociativity16Way;
  240. /* System level cache */
  241. mArmRdSmbiosType7[4].Base.MaximumCacheSize2 = 8192; // 8MB SLC per chip
  242. mArmRdSmbiosType7[4].Base.InstalledSize2 = 8192; // 8MB SLC per chip
  243. mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
  244. break;
  245. case RdE1Edge:
  246. /* L1 instruction cache */
  247. mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 32; // 32KB
  248. mArmRdSmbiosType7[0].Base.InstalledSize2 = 32; // 32KB
  249. mArmRdSmbiosType7[0].Base.Associativity = CacheAssociativity4Way;
  250. /* L1 data cache */
  251. mArmRdSmbiosType7[1].Base.MaximumCacheSize2 = 32; // 32KB
  252. mArmRdSmbiosType7[1].Base.InstalledSize2 = 32; // 32KB
  253. mArmRdSmbiosType7[1].Base.Associativity = CacheAssociativity4Way;
  254. /* L2 cache */
  255. mArmRdSmbiosType7[2].Base.MaximumCacheSize2 = 256; // 256KB
  256. mArmRdSmbiosType7[2].Base.InstalledSize2 = 256; // 256KB
  257. mArmRdSmbiosType7[2].Base.Associativity = CacheAssociativity4Way;
  258. /* L3 cache */
  259. mArmRdSmbiosType7[3].Base.MaximumCacheSize2 = 2048; // 2MB
  260. mArmRdSmbiosType7[3].Base.InstalledSize2 = 2048; // 2MB
  261. mArmRdSmbiosType7[3].Base.Associativity = CacheAssociativity16Way;
  262. /* System level cache */
  263. mArmRdSmbiosType7[4].Base.MaximumCacheSize2 = 8192; // 8MB SLC
  264. mArmRdSmbiosType7[4].Base.InstalledSize2 = 8192; // 8MB SLC
  265. mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
  266. break;
  267. case RdV1:
  268. case RdV1Mc:
  269. /* L1 instruction cache */
  270. mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64; // 64KB
  271. mArmRdSmbiosType7[0].Base.InstalledSize2 = 64; // 64KB
  272. mArmRdSmbiosType7[0].Base.Associativity = CacheAssociativity4Way;
  273. /* L1 data cache */
  274. mArmRdSmbiosType7[1].Base.MaximumCacheSize2 = 64; // 64KB
  275. mArmRdSmbiosType7[1].Base.InstalledSize2 = 64; // 64KB
  276. mArmRdSmbiosType7[1].Base.Associativity = CacheAssociativity4Way;
  277. /* L2 cache */
  278. mArmRdSmbiosType7[2].Base.MaximumCacheSize2 = 1024; // 1MB
  279. mArmRdSmbiosType7[2].Base.InstalledSize2 = 1024; // 1MB
  280. mArmRdSmbiosType7[2].Base.Associativity = CacheAssociativity8Way;
  281. /* System level cache */
  282. mArmRdSmbiosType7[4].Base.MaximumCacheSize2 = 16384; // 16MB SLC per chip
  283. mArmRdSmbiosType7[4].Base.InstalledSize2 = 16384; // 16MB SLC per chip
  284. mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
  285. break;
  286. case RdN2:
  287. case RdN2Cfg2:
  288. /* L1 instruction cache */
  289. mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64; // 64KB
  290. mArmRdSmbiosType7[0].Base.InstalledSize2 = 64; // 64KB
  291. mArmRdSmbiosType7[0].Base.Associativity = CacheAssociativity4Way;
  292. /* L1 data cache */
  293. mArmRdSmbiosType7[1].Base.MaximumCacheSize2 = 64; // 64KB
  294. mArmRdSmbiosType7[1].Base.InstalledSize2 = 64; // 64KB
  295. mArmRdSmbiosType7[1].Base.Associativity = CacheAssociativity4Way;
  296. /* L2 cache */
  297. mArmRdSmbiosType7[2].Base.MaximumCacheSize2 = 1024; // 1MB
  298. mArmRdSmbiosType7[2].Base.InstalledSize2 = 1024; // 1MB
  299. mArmRdSmbiosType7[2].Base.Associativity = CacheAssociativity8Way;
  300. /* System level cache */
  301. mArmRdSmbiosType7[4].Base.MaximumCacheSize2 = 32768; // 32MB SLC
  302. mArmRdSmbiosType7[4].Base.InstalledSize2 = 32768; // 32MB SLC
  303. mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
  304. break;
  305. case RdN2Cfg1:
  306. /* L1 instruction cache */
  307. mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64; // 64KB
  308. mArmRdSmbiosType7[0].Base.InstalledSize2 = 64; // 64KB
  309. mArmRdSmbiosType7[0].Base.Associativity = CacheAssociativity4Way;
  310. /* L1 data cache */
  311. mArmRdSmbiosType7[1].Base.MaximumCacheSize2 = 64; // 64KB
  312. mArmRdSmbiosType7[1].Base.InstalledSize2 = 64; // 64KB
  313. mArmRdSmbiosType7[1].Base.Associativity = CacheAssociativity4Way;
  314. /* L2 cache */
  315. mArmRdSmbiosType7[2].Base.MaximumCacheSize2 = 1024; // 1MB
  316. mArmRdSmbiosType7[2].Base.InstalledSize2 = 1024; // 1MB
  317. mArmRdSmbiosType7[2].Base.Associativity = CacheAssociativity8Way;
  318. /* System level cache */
  319. mArmRdSmbiosType7[4].Base.MaximumCacheSize2 = 8192; // 8MB SLC
  320. mArmRdSmbiosType7[4].Base.InstalledSize2 = 8192; // 8MB SLC
  321. mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
  322. break;
  323. }
  324. /* Install valid cache information tables */
  325. for (CacheIdx = 0; CacheIdx < ARRAY_SIZE (mArmRdSmbiosType7); CacheIdx++) {
  326. if (mArmRdSmbiosType7[CacheIdx].Base.MaximumCacheSize2 == 0) {
  327. continue;
  328. }
  329. SmbiosHandle = ((EFI_SMBIOS_TABLE_HEADER *)&mArmRdSmbiosType7[CacheIdx])->Handle;
  330. Status = Smbios->Add (
  331. Smbios,
  332. NULL,
  333. &SmbiosHandle,
  334. (EFI_SMBIOS_TABLE_HEADER *)&mArmRdSmbiosType7[CacheIdx]
  335. );
  336. if (EFI_ERROR (Status)) {
  337. DEBUG ((
  338. DEBUG_ERROR,
  339. "SMBIOS: Failed to install Type7 SMBIOS table.\n"
  340. ));
  341. }
  342. }
  343. return Status;
  344. }