Browse Source

WhitleyOpenBoardPkg : Support for Aowanda Platform

  - Created UBA for Aowanda platform
  - Disabled Intel ME IDE-R devices, KT devices  to reduce BIOS POST time
  - Modified build configuration file to support Aowanda platform build

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Cc: Sureshkumar Ponnusamy <sureshkumarp@ami.com>
Cc: Zachary Bobroff <zacharyb@ami.com>

Signed-off-by: Sureshkumar Ponnusamy <sureshkumarp@ami.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>
Sureshkumar Ponnusamy 1 year ago
parent
commit
e9c5be65fe
36 changed files with 3943 additions and 6 deletions
  1. 16 0
      Platform/Intel/Readme.md
  2. 47 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c
  3. 32 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf
  4. 93 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/PeiPlatformHookLib/PeiPlatformHooklib.c
  5. 35 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
  6. 82 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/PlatformPkg.dsc
  7. 827 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/PlatformPkg.fdf
  8. 99 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c
  9. 99 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h
  10. 49 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
  11. 112 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c
  12. 57 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h
  13. 49 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
  14. 128 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c
  15. 24 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h
  16. 45 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
  17. 54 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/AcpiTablePcds.c
  18. 329 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/GpioTable.c
  19. 186 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/IioBifurInit.c
  20. 86 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/KtiEparam.c
  21. 381 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PcdData.c
  22. 82 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PchEarlyUpdate.c
  23. 77 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PeiBoardInit.h
  24. 154 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PeiBoardInitLib.c
  25. 167 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PeiBoardInitLib.inf
  26. 167 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/SlotTable.c
  27. 73 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/SoftStrapFixup.c
  28. 124 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/UsbOC.c
  29. 195 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/build_board.py
  30. 52 0
      Platform/Intel/WhitleyOpenBoardPkg/Aowanda/build_config.cfg
  31. 2 1
      Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
  32. 11 1
      Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c
  33. 2 1
      Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf
  34. 3 1
      Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf
  35. 2 1
      Platform/Intel/build.cfg
  36. 2 1
      Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h

+ 16 - 0
Platform/Intel/Readme.md

@@ -96,6 +96,7 @@ A UEFI firmware implementation using MinPlatformPkg is constructed using the fol
 
 | Machine Name                          | Supported Chipsets                         | BoardPkg                     | Board Name         |
 ----------------------------------------|--------------------------------------------|------------------------------|--------------------|
+| Aowanda                               | IceLake-SP (Xeon Scalable)                 | WhitleyOpenBoardPkg          | Aowanda            |
 | Junction City                         | IceLake-SP (Xeon Scalable)                 | WhitleyOpenBoardPkg          | JunctionCity       |
 | Mt. Olympus                           | Purley                                     | PurleyOpenBoardPkg           | BoardMtOlympus     |
 | TiogaPass                             | Purley                                     | PurleyOpenBoardPkg           | BoardTiogaPass     |
@@ -276,6 +277,11 @@ return back to the minimum platform caller.
           |       |        |                                     build settings, environment variables.
           |       |        |
           |       |        |------WhitleyOpenBoardPkg
+          |       |        |       |------Aowanda
+          |       |        |       |       |---build_config.cfg: Aowanda  specific build
+          |       |        |       |       |                     settings environment variables.
+          |       |        |       |       |---build_board.py: Board-specific pre-build,
+          |       |        |       |                           build, post-build and clean functions.
           |       |        |       |------CooperCityRvp
           |       |        |       |       |---build_config.cfg: CooperCityRvp specific build
           |       |        |       |       |                     settings environment variables.
@@ -406,6 +412,16 @@ For PurleyOpenBoardPkg (TiogaPass)
 5. Connected PCIE Network card and made sure PCIE card detected in POST and in OS
 6. Verified TPM offboard chip detection
 
+**Aowanda**
+1. This firmware project has been tested booting to UEFI shell
+2. Installed and booted to RHEL 8.3 using M2 SSD disk
+3. Installed and booted to Windows 2019 using M2 SSD disk
+4. Verified TPM chip detection
+
+Note:
+For the network boot using the onboard Intel network card, please download the UEFI UNDI driver (E9712X3.efi) from https://www.intel.com/content/www/us/en/download/15755/intel-ethernet-connections-boot-utility-preboot-images-and-efi-drivers.html
+and include it in PlatformPkg.fdf.
+
 ### **Package Builds**
 
 In some cases, such as BoardModulePkg, a package may provide a set of functionality that is included in other

+ 47 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c

@@ -0,0 +1,47 @@
+/** @file
+  This file implements the IPMI Platform hook functions
+
+  Copyright (c) 2021, American Megatrends International LLC. <BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+
+#define KCS_BASE_ADDRESS_MASK      0xFFF0
+#define NUMBER_OF_BYTES_TO_DECODE  0x10
+
+/**
+  This function sets IO Decode Range in LPC registers
+
+  @param[in]  IpmiIoBase  - IPMI Base IO address
+
+  @retval  EFI_SUCCESS    - Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformIpmiIoRangeSet (
+  UINT16  IpmiIoBase
+  )
+{
+  EFI_STATUS             Status;
+  DYNAMIC_SI_LIBARY_PPI  *DynamicSiLibraryPpi;
+
+  DynamicSiLibraryPpi = NULL;
+
+  DEBUG ((DEBUG_INFO, "PlatformIpmiIoRangeSet IpmiIoBase %x\n", IpmiIoBase));
+
+  Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "PeiServicesLocatePpi for gDynamicSiLibraryPpiGuid failed. Status %r\n", Status));
+    ASSERT_EFI_ERROR (Status);
+    return Status;
+  }
+
+  DynamicSiLibraryPpi->PchLpcGenIoRangeSet ((IpmiIoBase & KCS_BASE_ADDRESS_MASK), NUMBER_OF_BYTES_TO_DECODE);
+  return EFI_SUCCESS;
+}

+ 32 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf

@@ -0,0 +1,32 @@
+## @file
+# Component description file for IPMI platform hook Library.
+#
+# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2021, American Megatrends International LLC.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = IpmiPlatformHookLib
+  FILE_GUID                      = A770BDB8-331A-4110-8B60-81FC17480B36
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = IpmiPlatformHookLib
+
+[sources]
+  IpmiPlatformHookLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  WhitleySiliconPkg/WhitleySiliconPkg.dec
+
+[LibraryClasses]
+  DebugLib
+
+[Ppis]
+  gDynamicSiLibraryPpiGuid                 ## CONSUMES
+
+[Depex]
+  gDynamicSiLibraryPpiGuid

+ 93 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/PeiPlatformHookLib/PeiPlatformHooklib.c

@@ -0,0 +1,93 @@
+/** @file
+  PEI Library Functions. Initialize GPIOs
+
+  Copyright 1999 - 2021 Intel Corporation. <BR>
+  Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Uefi.h>
+#include <Guid/PlatformInfo.h>
+#include <Library/DebugLib.h>
+#include <Library/UbaGpioInitLib.h>
+#include <Library/PeiPlatformHooklib.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+/**
+  Configure GPIO
+
+  @param[in]  None
+
+  @retval     None
+**/
+VOID
+GpioInit (
+  VOID
+  )
+{
+  PlatformInitGpios ();
+}
+
+/**
+  Disables ME PCI devices like IDE-R , KT
+
+  @param[in]  None
+  @retval  EFI_SUCCESS   Operation success.
+
+**/
+EFI_STATUS
+DisableMEDevices (
+  VOID
+  )
+{
+  EFI_STATUS             Status = EFI_SUCCESS;
+  DYNAMIC_SI_LIBARY_PPI  *DynamicSiLibraryPpi;
+
+  DynamicSiLibraryPpi = NULL;
+
+  DEBUG ((DEBUG_INFO, "DisableMEDevices\n"));
+
+  Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+  if (EFI_ERROR (Status)) {
+    ASSERT_EFI_ERROR (Status);
+    return Status;
+  }
+
+  //
+  // Disable IDE-R
+  //
+  DynamicSiLibraryPpi->PchPcrAndThenOr32 (
+                         PID_PSF1,
+                         (R_PCH_H_PCR_PSF1_T0_SHDW_IDER_REG_BASE + R_PCH_PSFX_PCR_T0_SHDW_PCIEN),
+                         (UINT32)~0,
+                         B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS
+                         );
+
+  //
+  // Disable KT
+  //
+  DynamicSiLibraryPpi->PchPcrAndThenOr32 (
+                         PID_PSF1,
+                         (R_PCH_H_PCR_PSF1_T0_SHDW_KT_REG_BASE + R_PCH_PSFX_PCR_T0_SHDW_PCIEN),
+                         (UINT32)~0,
+                         B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS
+                         );
+  return EFI_SUCCESS;
+}
+
+/**
+  Configure GPIO and SIO
+
+  @retval  EFI_SUCCESS   Operation success.
+**/
+EFI_STATUS
+BoardInit (
+  )
+{
+  GpioInit ();
+  DisableMEDevices ();
+
+  return EFI_SUCCESS;
+}

+ 35 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf

@@ -0,0 +1,35 @@
+## @file
+#
+# @copyright
+# Copyright 1999 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PeiPlatformHookLib
+  FILE_GUID                      = 6E9351C3-A17A-4ADF-8602-55B07962718F
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = PeiPlatformHookLib|PEIM PEI_CORE SEC
+
+[Sources]
+  PeiPlatformHooklib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  WhitleyOpenBoardPkg/PlatformPkg.dec
+  WhitleySiliconPkg/WhitleySiliconPkg.dec
+  WhitleySiliconPkg/CpRcPkg.dec
+
+[LibraryClasses]
+  DebugLib
+  UbaGpioInitLib
+
+[Pcd]
+
+[Ppis]
+
+[Guids]

+ 82 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/PlatformPkg.dsc

@@ -0,0 +1,82 @@
+## @file
+# DSC file of Aowanda platform
+#
+# @copyright
+# Copyright 2008 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2022, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PEI_ARCH                            = IA32
+  DXE_ARCH                            = X64
+
+  !include WhitleyOpenBoardPkg/PlatformPkg.dsc
+
+[PcdsFixedAtBuild]
+  gMinPlatformPkgTokenSpaceGuid.PcdBootStage|6
+
+[PcdsFeatureFlag]
+!if $(gMinPlatformPkgTokenSpaceGuid.PcdBootStage) >= 5
+  gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable        |TRUE
+  gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable  |TRUE
+!else
+  gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable        |FALSE
+  gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable  |FALSE
+!endif
+
+  !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc
+
+[Defines]
+  BOARD_NAME                = Aowanda
+  PLATFORM_NAME             = $(BOARD_NAME)
+  PLATFORM_GUID             = 240D6B04-AFED-47E7-AB05-64B621A1112D
+  FLASH_DEFINITION          = $(RP_PKG)/$(BOARD_NAME)/PlatformPkg.fdf
+
+[PcdsFixedAtBuild]
+
+!if $(TARGET) == "RELEASE"
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F                   # Enable asserts, prints, code, clear memory, and deadloops on asserts.
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x80200047      # Built in messages:  Error, MTRR, info, load, warn, init
+  gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2     # This is set to INT3 (0x2) for Simics source level debugging
+!endif
+  gPlatformTokenSpaceGuid.PcdBoardId|0x26
+
+[PcdsFixedAtBuild.X64]
+  gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|1900
+  gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|9999
+
+[PcdsDynamicExHii]
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
+
+[LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]
+  PeiPlatformHookLib|$(RP_PKG)/$(BOARD_NAME)/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
+
+!if gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable == TRUE
+  IpmiPlatformHookLib| $(RP_PKG)/$(BOARD_NAME)/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf
+!endif
+
+[Components.IA32]
+  $(RP_PKG)/Uba/BoardInit/Pei/BoardInitPei.inf {
+    <LibraryClasses>
+      NULL|$(RP_PKG)/$(BOARD_NAME)/Uba/TypeAowanda/Pei/PeiBoardInitLib.inf
+      NULL|$(RP_PKG)/Uba/UbaMain/Common/Pei/PeiCommonBoardInitLib.inf
+  }
+
+[Components.X64]
+  $(RP_PKG)/$(BOARD_NAME)/Uba/TypeAowanda/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
+  $(RP_PKG)/$(BOARD_NAME)/Uba/TypeAowanda/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
+  $(RP_PKG)/$(BOARD_NAME)/Uba/TypeAowanda/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
+  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf

+ 827 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/PlatformPkg.fdf

@@ -0,0 +1,827 @@
+## @file
+# FDF file of Aowanda platform
+# This package provides platform specific modules and flash layout information.
+#
+# @copyright
+# Copyright 2006 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2022, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+DEFINE PLATFORM_PKG             = MinPlatformPkg
+
+# 0x00000060 = (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_FFS_FILE_HEADER))
+DEFINE FDF_FIRMWARE_HEADER_SIZE = 0x00000060
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv              = 0x90 # FV Header plus FFS header
+
+DEFINE VPD_HEADER_SIZE = 0x00000090
+
+!if $(FSP_MODE) == 0
+  DEFINE FSP_BIN_DIR = Api
+!else
+  DEFINE FSP_BIN_DIR = Dispatch
+!endif
+
+#
+# Note: FlashNv PCD naming conventions are as follows:
+#        Note: This should be 100% true of all PCD's in the gCpPlatFlashTokenSpaceGuid space, and for
+#              Others should be examined with an effort to work toward this guideline.
+#       PcdFlash*Base is an address, usually in the range of 0xf* of FD's, note change in FDF spec
+#       PcdFlash*Size is a hex count of the length of the FD or FV
+#       All Fv will have the form 'PcdFlashFv', and all Fd will have the form 'PcdFlashFd'
+#
+#       Also all values will have a PCD assigned so that they can be used in the system, and
+#       the FlashMap edit tool can be used to change the values here, without effecting the code.
+#       This requires all code to only use the PCD tokens to recover the values.
+
+
+#
+# 16MiB Total FLASH Image (visible in memory mapped IO)
+#
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress  = 0xFF000000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize         = 0x01000000
+
+################################################################################
+#
+#    FD SECPEI
+#
+# Contains all the SEC and PEI modules
+#
+# Layout: (Low address to high address)
+#
+#     FvBsp for board specific components
+#     FvPostMemory for compressed post memory MinPlatform spec required components
+#     FvFspS for compressed post memory silicon initialization components
+#       FvPostMemorySilicon for silicon components
+#     FvFspM for pre memory silicon initialization components
+#       FvPreMemorySilicon for silicon components
+#     FvFspT for temp RAM silicon initilization components
+#     FvBspPreMemory for board specific components required to intialize memory
+#       FvAdvancedPreMemory FV for advanced features components
+#     FvPreMemory for components required by MinPlatform spec and to initialize memory
+#       FvPreMemorySecurity FV for stage 6 required components
+#       Contains reset vector
+#
+################################################################################
+
+[FD.SecPei]
+  BaseAddress   = 0xFFCA0000   |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase                 #The base address of the FLASH Device
+  Size          = 0x00360000   |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize                 #The size in bytes of the FLASH Device
+  ErasePolarity = 1
+  BlockSize     = 0x1000
+  NumBlocks     = 0x360
+
+  #
+  # These must add up to the FD Size.
+  # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
+  # At this time, the FSP FV must be aligned at the same address they were built to, 0xFFD00000
+  # This will be corrected in the future.
+  #
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize           = 0x00010000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must = 0xFFD00000
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize    = 0x00010000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must = 0xFFD00000
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize          = 0x00040000 # Size must match WhitleyFspPkg.fdf content
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize          = 0x00221000 # Size must match WhitleyFspPkg.fdf content
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize          = 0x00006000 # Size must match WhitleyFspPkg.fdf content
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize  = 0x00009000
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize     = gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+
+  #
+  # Calculate Offsets Once (Do not modify)
+  # This layout is specified by the EDK II Minimum Platform Archicture specification.
+  # Each offset is the prior region's offset plus the prior region's size.
+  #
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset           = 0x00000000
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset    = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset           + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset          = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset    + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset          = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset          + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset          = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset          + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset  = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset          + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset     = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset  + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+
+  #
+  # FV Layout (Do not modify)
+  # This layout is specified by the EDK II Minimum Platform Archicture specification.
+  #
+
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
+  FV = FvBsp
+
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+  FV = FvPostMemory
+
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+  FILE = $(FSP_BIN_PKG)/Fsp_Rebased_S.fd
+
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+  FILE = $(FSP_BIN_PKG)/Fsp_Rebased_M.fd
+
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+  FILE = $(FSP_BIN_PKG)/Fsp_Rebased_T.fd
+
+  #
+  # Shared FV layout
+  #
+
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+  FV = FvBspPreMemory
+
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
+  FV = FvPreMemory
+
+  #
+  # Calculate base addresses (Do not modify)
+  # This layout is specified by the EDK II Minimum Platform Archicture specification.
+  # Each base is the prior region's base plus the prior region's size.
+  #
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase             = gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase      = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase            = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase            = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase            = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase    = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase       = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+
+  #
+  # Set duplicate PCD
+  # These should not need to be changed
+  #
+
+  SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
+  SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+  SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase    = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase
+  SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize    = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
+
+  #
+  # For API mode, wrappers have some duplicate PCD as well
+  #
+  SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase
+  SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
+  SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase
+
+################################################################################
+#
+#    FD Main
+#
+# All DXE modules and other regions
+#
+# Layout: (Low address to high address)
+#
+#     FvAdvanced for advanced feature components
+#       Assorted advanced feature FV
+#     FvSecurity for MinPlatform spec required components needed to boot securely
+#     FvOsBoot for MinPlatform spec required components needed to boot OS
+#       FvLateSilicon for silicon specific components
+#     FvUefiBoot for MinPlatform spec required components needed to boot to UEFI shell
+#
+################################################################################
+[FD.Main]
+  BaseAddress   = 0xFF2E0000     | gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase        # The base address of the FLASH Device
+  Size          = 0x009C0000     | gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize        # The size in bytes of the FLASH Device
+  ErasePolarity = 1
+  BlockSize     = 0x1000
+  NumBlocks     = 0x9C0
+
+  #
+  # These must add up to the FD Size.
+  # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
+  # These are out of flash layout order because FvAdvanced gets any remaining space
+  #
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize      = 0x00040000
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize        = 0x00230000
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize      = 0x0004C000
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize      = gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+
+  #
+  # Calculate Offsets Once (Do not modify)
+  # This layout is specified by the EDK II Minimum Platform Archicture specification.
+  # Each offset is the prior region's offset plus the prior region's size.
+  #
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset    = 0x00000000
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset    = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset  + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset      = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset  + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset    = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset    + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+
+  #
+  # FV Layout (Do not modify)
+  # This layout is specified by the EDK II Minimum Platform Archicture specification.
+  #
+
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+  FV = FvAdvanced
+
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+  FV = FvSecurity
+
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+  FV = FvOsBoot
+
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
+  FV = FvUefiBoot
+
+  #
+  # Calculate base addresses (Do not modify)
+  # This layout is specified by the EDK II Minimum Platform Archicture specification.
+  # Each base is the prior region's base plus the prior region's size.
+  #
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase      = gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase         + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase      = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase  + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase        = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase  + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase      = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase    + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+
+################################################################################
+#
+#    FD BINARY
+#
+# Contains the OPROM and other binary modules
+#
+# Layout: (Low address to high address)
+#
+#     FvOpRom containing pre-built components
+#     FvAcmRegion containing ACM related content
+#       FV Header + Blank Space (1K)
+#       Policy block (3K)
+#       Blank space to align ACM on 64K boundary (60K)
+#       ACM binary
+#     FvMicrocode containing microcode update patches
+#     Unformatted region for PCI Gen 3 Data
+#     FvVpd containing PCD VPD data
+#     FvWhea for WHEA data recording
+#     FvNvStorageVariable for UEFI Variable storage
+#     FvNvStorageEventLog for NV Store management
+#     FvNvStorageFtwWorking for Fault Tolerant Write solution
+#     FvNvStorageFtwSpare for Fault Tolerant Write solution
+#
+################################################################################
+[FD.Binary]
+  BaseAddress   = 0xFF000000   |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase
+  Size          = 0x002E0000   |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinarySize
+  ErasePolarity = 1
+  BlockSize     = 0x1000
+  NumBlocks     = 0x2E0
+
+  #
+  # These must add up to the FD Size.
+  # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
+  #
+  SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize                  = 0x00100000
+  SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize              = 0x00050000
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize           = 0x000D0000
+  SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize                 = 0x00010000
+  SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize                   = 0x00030000
+  #
+  # These four items are tightly coupled.
+  # The spare area size must be >= the first three areas.
+  #
+  # There isn't really a benefit to a larger spare area unless the FLASH device
+  # block size is larger than the size specified.
+  #
+  SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize    = 0x0003C000
+  SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize      = 0x00002000
+  SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize  = 0x00002000
+  SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize    = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+  #
+  # Calculate Offsets Once (You should not need to modify this section)
+  # Each offset is the prior region's offset plus the prior region's size.
+  #
+  SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset                  = 0x00000000
+  SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset              = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset                + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset           = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset            + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
+  SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset                 = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset         + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
+  SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset                   = gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset               + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset     = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset                 + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
+  SET gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset   = gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset   + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset   = gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset     = gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+  #
+  # Set gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress dynamically
+  #
+  SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress             = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase                 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset         + gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv
+  SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize          = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize           - gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv
+
+  #
+  # FV Layout (You should not need to modify this section)
+  #
+  gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+  FV = FvOprom
+
+  gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
+  FV = FvAcm
+
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
+  FV = FvMicrocode
+
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize
+  FV = FvVPD
+
+  gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
+  FV = FvWhea
+
+  #
+  # Do not modify.
+  # See comments in size discussion above.  These four areas are tightly coupled and should be modified with utmost care.
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+  !include WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
+  DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as Base/Size to be written
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+  !include WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorageFtwWorking.fdf
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+  DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as Base/Size to be written
+
+  #
+  # Calculate base addresses (You should not need to modify this section)
+  # Each base is the prior region's base plus the prior region's size.
+  #
+  SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase                  = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase                 + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset
+  SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase              = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase                  + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase           = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase              + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
+  SET gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress                = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase           + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + $(VPD_HEADER_SIZE)
+  SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase                   = gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress                + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize - $(VPD_HEADER_SIZE)
+  SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase    = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase                   + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
+  SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase      = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase    + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+  SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase  = gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase      + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
+  SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase    = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase  + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+  #
+  # ACM details
+  #
+  SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase      = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x1000
+  SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize      = 0x3000
+  SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase            = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x10000
+  SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize            = 0x00040000
+
+  #
+  # Other duplicate PCD
+  #
+  SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+  SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
+  SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase  = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase
+  SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize  = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
+################################################################################
+#
+#    FD FPGA
+#
+# Contains the FPGA modules
+#
+################################################################################
+
+[FD.Fpga]
+  BaseAddress   = 0xFD000000   |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaBase                 #The base address of the FPGA Device ( 4G - 48M )
+  Size          = 0x02000000   |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaSize                 #The size in bytes of the FPGA Device ( 32M )
+  ErasePolarity = 1
+  BlockSize     = 0x1000
+  NumBlocks     = 0x2000
+
+  0x00000000|0x02000000
+  gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase | gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsSize
+  FV = FvFpga
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvSecurityPreMemory]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = 40ab290f-8494-41cf-b302-31b178b4ce0b
+
+  !include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
+
+[FV.FvPreMemory]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = 6522280D-28F9-4131-ADC4-F40EBFA45864
+
+  INF  UefiCpuPkg/SecCore/SecCore.inf
+  INF  MdeModulePkg/Core/Pei/PeiMain.inf
+
+  INF  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+  INF  WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.inf
+  INF  WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf
+
+  INF  UefiCpuPkg/CpuIoPei/CpuIoPei.inf
+
+  INF  MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+  INF  MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+
+  INF  WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf
+
+  INF  WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf
+
+  FILE PEIM = ac4b7f1b-e057-47d3-b2b5-1137493c0f38 {
+    SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.depex
+    SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.efi
+    SECTION UI = "DynamicSiLibraryPei"
+  }
+
+  INF  WhitleyOpenBoardPkg/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.inf
+
+  INF  WhitleyOpenBoardPkg/Platform/Pei/EmulationPlatformInit/EmulationPlatformInit.inf
+
+  INF  WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.inf
+
+  #
+  # UBA common and board specific components
+  #
+  !include WhitleyOpenBoardPkg/Uba/UbaPei.fdf
+
+  INF  MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+
+  INF  MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf
+
+  FILE PEIM = ca8efb69-d7dc-4e94-aad6-9fb373649161 {
+    SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.depex
+    SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.efi
+    SECTION UI = "SiliconPolicyInitPreAndPostMem"
+  }
+
+  INF  MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
+
+  !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePreMemory.fdf
+
+  INF WhitleyOpenBoardPkg/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf
+
+  INF  RuleOverride = LzmaCompress UefiCpuPkg/CpuMpPei/CpuMpPei.inf
+
+  !if $(FSP_MODE) == 0
+    FILE PEIM = 8F7F3D20-9823-42DD-9FF7-53DAC93EF407 {
+      SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.depex
+      SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.efi
+      SECTION UI = "CsrPseudoOffsetInitPeim"
+    }
+    FILE PEIM = 2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352 {
+      SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.depex
+      SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.efi
+      SECTION UI = "RegAccessPeim"
+    }
+    FILE PEIM = C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67F {
+      SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.depex
+      SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.efi
+      SECTION UI = "SiliconDataInitPeim"
+    }
+    INF  IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+    INF  IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+    INF  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+    INF  WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi/DummyPchSpi.inf
+  !endif
+
+  FILE FV_IMAGE = 40ab290f-8494-41cf-b302-31b178b4ce0b {
+    SECTION FV_IMAGE = FvSecurityPreMemory
+  }
+
+[FV.FvAdvancedPreMemory]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = 09f25d44-b2ef-4225-8b2e-e0e094b51775
+
+  !include AdvancedFeaturePkg/Include/PreMemory.fdf
+
+[FV.FvBspPreMemory]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = e6c65995-8c2d-4119-a52d-7dbf1acb45a1
+
+  FILE FV_IMAGE = 09f25d44-b2ef-4225-8b2e-e0e094b51775 {
+    SECTION FV_IMAGE = FvAdvancedPreMemory
+  }
+
+#
+# FvPostMemory includes common hardware, common core variable services, load and invoke DXE etc
+#
+[FV.FvPostMemoryUncompressed]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA
+
+[FV.FvPostMemory]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = 3298afc4-c484-47f1-a65a-5917a54b5e8c
+
+  FILE FV_IMAGE = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FvPostMemoryUncompressed
+    }
+  }
+
+#
+# FvBsp includes board specific components
+#
+[FV.FvBspUncompressed]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = e4c65347-fd90-4143-8a41-113e1015fe07
+
+[FV.FvBsp]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = 9e151cf3-ca90-444f-b33b-a9941cbc772f
+
+  FILE FV_IMAGE = e4c65347-fd90-4143-8a41-113e1015fe07 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FvBspUncompressed
+    }
+  }
+
+[FV.FvUefiBootUncompressed]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = C4D3B0E2-FB26-44f8-A05B-E95895FCB960
+
+  INF  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  INF  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  INF  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+  INF  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+  INF  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  INF  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+  INF  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  INF  MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe.inf
+
+  INF  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  INF  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  INF  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+  INF  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  INF  MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf
+  #ATA for IDE/AHCI/RAID support
+  INF  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+  INF  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF  MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+  INF  BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
+  INF  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+
+  FILE DRIVER = 85299F8F-F2B9-4487-AF60-231434A5EFF6 {
+    SECTION PE32 = edk2-non-osi/Drivers/ASpeed/ASpeedGopBinPkg/X64/ASpeedAst2600Gop.efi
+  }
+
+
+[FV.FvUefiBoot]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = ab9fe87b-1e37-440c-91cc-9aea03ce7bec
+
+  FILE FV_IMAGE = C4D3B0E2-FB26-44f8-A05B-E95895FCB960 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FvUefiBootUncompressed
+    }
+  }
+
+[FV.FvOsBootUncompressed]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0
+
+  #
+  #  DXE Phase modules
+  #
+  INF  MdeModulePkg/Core/Dxe/DxeMain.inf
+  INF  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+  INF  MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+  INF  MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+
+  FILE FV_IMAGE = B7C9F0CB-15D8-26FC-CA3F-C63947B12831 {
+    SECTION UI = "FvLateSilicon"
+    SECTION FV_IMAGE = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateSilicon.fv
+  }
+
+  INF  MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf
+
+  !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePostMemory.fdf
+
+  #
+  # UBA DXE common and board specific components
+  #
+  !include WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf
+  INF $(RP_PKG)/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf
+  INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeAowanda/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
+  INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeAowanda/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
+  INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeAowanda/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
+  INF  WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/PlatformType.inf
+  INF  MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
+
+  !if ($(FSP_MODE) == 1)
+    INF WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSave.inf
+  !else
+    INF MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
+  !endif
+
+  INF  UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+  INF  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+  INF  WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf
+  INF  UefiCpuPkg/CpuDxe/CpuDxe.inf
+  INF  UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
+
+  FILE FV_IMAGE = a0277d07-a725-4823-90f9-6cba00782111 {
+    SECTION UI = "FvLateOpenBoard"
+    SECTION FV_IMAGE = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateOpenBoard.fv
+  }
+
+  INF  MdeModulePkg/Universal/Metronome/Metronome.inf
+  INF  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+  INF  PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
+  INF  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+  INF  WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf
+  INF  MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
+
+  INF  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  INF  RuleOverride = UI MdeModulePkg/Application/UiApp/UiApp.inf
+  INF  MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
+  INF  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  #TPM when TPM enable, SecurityStubDxe needs to be removed from this FV.
+  INF  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+
+  INF  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+
+  INF  FatPkg/EnhancedFatDxe/Fat.inf
+
+  INF  PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+
+  INF  WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPlatform.inf
+  INF  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  INF  ShellPkg/Application/Shell/Shell.inf
+
+  INF  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+
+  INF  MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
+  INF  MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
+
+  INF  MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
+  INF  MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf
+
+  INF  UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
+
+  INF  MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
+  INF  UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
+
+  INF  IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+
+  INF  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
+  INF  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf
+  INF  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf
+
+  INF  MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf
+
+  INF  MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+
+  INF  MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
+
+  # UEFI USB stack
+  INF  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+  INF  MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf
+  INF  BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
+  INF  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+
+  INF  RuleOverride = ACPITABLE WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTables10nm.inf
+  INF  WhitleyOpenBoardPkg/Features/Acpi/AcpiPlatform/AcpiPlatform.inf
+  INF  WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf
+  INF  MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf
+
+[FV.FvOsBoot]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = c7488640-5f51-4969-b63b-89fc369e1725
+
+  FILE FV_IMAGE = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FvOsBootUncompressed
+    }
+  }
+
+[FV.FvSecuritySilicon]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = AD262F8D-BDED-4668-A8D4-8BC73516652F
+
+  !include MinPlatformPkg/Include/Fdf/CoreSecurityLateInclude.fdf
+
+[FV.FvSecurityUncompressed]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = 03E25550-89A5-4ee6-AF60-DB0553D91FD2
+
+  FILE FV_IMAGE = 81F80AEA-91EB-4AD9-A563-7CEBAA167B25 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FvSecuritySilicon
+    }
+  }
+
+[FV.FvSecurity]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = 68134833-2ff6-4d22-973b-575d0eae8ffd
+
+  FILE FV_IMAGE = 03E25550-89A5-4ee6-AF60-DB0553D91FD2 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+        SECTION FV_IMAGE = FvSecurityUncompressed
+    }
+  }
+
+[FV.FvAdvancedUncompressed]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = 70aeaf57-4997-49ce-a4f7-122980745670
+
+  !include AdvancedFeaturePkg/Include/PostMemory.fdf
+
+[FV.FvAdvanced]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = f21ee7a1-53a9-453d-aee3-b6a5c25bada5
+
+  FILE FV_IMAGE = 70aeaf57-4997-49ce-a4f7-122980745670 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FvAdvancedUncompressed
+    }
+  }
+
+#
+# FV for all Microcode Updates.
+#
+[FV.FvMicrocode]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  LOCK_STATUS        = FALSE
+  FvNameGuid         = D2C29BA7-3809-480F-9C3D-DE389C61425A
+
+!if $(CPUTARGET) == "CPX"
+  INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/MicrocodeUpdates.inf
+!else
+  INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/MicrocodeUpdates.inf
+!endif
+
+
+[FV.FvVPD]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  LOCK_STATUS        = FALSE
+  FvNameGuid         = FFC29BA7-3809-480F-9C3D-DE389C61425A
+  FILE RAW = FF7DB236-F856-4924-90F8-CDF12FB875F3 {
+    $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/8C3D856A-9BE6-468E-850A-24F7A8D38E08.bin
+  }
+
+#
+# Various Vendor UEFI Drivers (OROMs).
+#
+[FV.FvOpromUncompressed]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = B6EDE22C-DE30-45fa-BB09-CA202C1654B7
+
+[FV.FvOprom]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = 983BCAB5-BF10-42ce-B85D-CB805DCB1EFD
+
+  FILE FV_IMAGE = B6EDE22C-DE30-45fa-BB09-CA202C1654B7 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FvOpromUncompressed
+    }
+  }
+
+[FV.FvWhea]
+  BlockSize          = 0x1000
+  NumBlocks          = 0x30
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = d6a1cd70-4b33-4994-a6ea-375f2ccc5437
+
+#
+# FV For ACM Binary.
+#
+[FV.FvAcm]
+  BlockSize          = 0x1000
+  NumBlocks          = 0x50
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = 11668261-8A8D-47ca-9893-052D24435E59
+
+[FV.FvFpga]
+  !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+  FvNameGuid         = 974650E7-6DFE-4998-A124-CEDEC5C9B47D
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI    Optional           |.acpi
+    RAW ASL     Optional           |.aml
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER.DRIVER_ACPITABLE]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    RAW ACPI  Optional                |.acpi
+    RAW ASL   Optional                |.aml
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }

+ 99 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c

@@ -0,0 +1,99 @@
+/** @file
+  IIO Config Update.
+
+  @copyright
+  Copyright 2018 - 2021 Intel Corporation. <BR>
+  Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "IioCfgUpdateDxe.h"
+
+EFI_STATUS
+UpdateAowandaIioConfig (
+  IN  IIO_GLOBALS  *IioGlobalData
+  )
+{
+  return EFI_SUCCESS;
+}
+
+PLATFORM_IIO_CONFIG_UPDATE_TABLE  TypeAowandaIioConfigTable =
+{
+  PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE,
+  PLATFORM_IIO_CONFIG_UPDATE_VERSION,
+
+  IioBifurcationTable,
+  sizeof (IioBifurcationTable),
+  UpdateAowandaIioConfig,
+  IioSlotTable,
+  sizeof (IioSlotTable)
+};
+
+/**
+  The Driver Entry Point.
+
+  The function is the driver Entry point.
+
+  @param ImageHandle   A handle for the image that is initializing this driver
+  @param SystemTable   A pointer to the EFI system table
+
+  @retval EFI_SUCCESS:              Driver initialized successfully
+  @retval EFI_LOAD_ERROR:           Failed to Initialize or has been loaded
+  @retval EFI_OUT_OF_RESOURCES      Could not allocate needed resources
+
+**/
+EFI_STATUS
+EFIAPI
+IioCfgUpdateEntry (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EFI_STATUS                    Status;
+  UBA_CONFIG_DATABASE_PROTOCOL  *UbaConfigProtocol = NULL;
+
+  DEBUG ((EFI_D_INFO, "UBA:IioCfgUpdate-TypeAowanda\n"));
+  Status = gBS->LocateProtocol (
+                  &gUbaConfigDatabaseProtocolGuid,
+                  NULL,
+                  &UbaConfigProtocol
+                  );
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  Status = UbaConfigProtocol->AddData (
+                                     UbaConfigProtocol,
+                                     &gPlatformIioConfigDataDxeGuid,
+                                     &TypeAowandaIioConfigTable,
+                                     sizeof(TypeAowandaIioConfigTable)
+                                     );
+
+  Status = UbaConfigProtocol->AddData (
+                                     UbaConfigProtocol,
+                                     &gPlatformIioConfigDataDxeGuid_1,
+                                     &TypeAowandaIioConfigTable,
+                                     sizeof(TypeAowandaIioConfigTable)
+                                     );
+
+  Status = UbaConfigProtocol->AddData (
+                                     UbaConfigProtocol,
+                                     &gPlatformIioConfigDataDxeGuid_2,
+                                     &TypeAowandaIioConfigTable,
+                                     sizeof(TypeAowandaIioConfigTable)
+                                     );
+
+  Status = UbaConfigProtocol->AddData (
+                                     UbaConfigProtocol,
+                                     &gPlatformIioConfigDataDxeGuid_3,
+                                     &TypeAowandaIioConfigTable,
+                                     sizeof(TypeAowandaIioConfigTable)
+                                     );
+
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  return Status;
+}

+ 99 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h

@@ -0,0 +1,99 @@
+/** @file
+
+  @copyright
+  Copyright 2016 - 2021 Intel Corporation. <BR>
+  Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IIOCFG_UPDATE_DXE_H_
+#define _IIOCFG_UPDATE_DXE_H_
+
+#include <Base.h>
+#include <Uefi.h>
+#include <Protocol/UbaCfgDb.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PciLib.h>
+#include <Library/UbaIioConfigLib.h>
+#include <IioPlatformData.h>
+
+typedef enum {
+  Iio_Socket0 = 0,
+  Iio_Socket1,
+  Iio_Socket2,
+  Iio_Socket3,
+  Iio_Socket4,
+  Iio_Socket5,
+  Iio_Socket6,
+  Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+  Iio_Iou0 = 0,
+  Iio_Iou1,
+  Iio_Iou2,
+  Iio_Mcp0,
+  Iio_Mcp1,
+  Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+  VPP_PORT_0 = 0,
+  VPP_PORT_1,
+  VPP_PORT_2,
+  VPP_PORT_3
+} VPP_PORT;
+
+#define ENABLE        1
+#define DISABLE       0
+#define NO_SLT_IMP    0xFF
+#define SLT_IMP       1
+#define HIDE          1
+#define NOT_HIDE      0
+#define VPP_PORT_0    0
+#define VPP_PORT_1    1
+#define VPP_PORT_MAX  0xFF
+#define VPP_ADDR_MAX  0xFF
+#define PWR_VAL_MAX   0xFF
+#define PWR_SCL_MAX   0xFF
+
+static IIO_BIFURCATION_DATA_ENTRY  IioBifurcationTable[] =
+{
+  { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 },
+  { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 },
+  { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 },
+  { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 },
+  { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 },
+  { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxx8xxx8 },
+  { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 },
+  { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 },
+  { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 },
+  { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 },
+};
+
+static IIO_SLOT_CONFIG_DATA_ENTRY   IioSlotTable[] = {
+  // Port        |  Slot      | Inter      | Power Limit | Power Limit | Hot     | Vpp          | Vpp          | PcieSSD | PcieSSD     | PcieSSD       | Hidden
+  // Index       |            | lock       | Scale       |  Value      | Plug    | Port         | Addr         | Cap     | VppPort     | VppAddr       |
+  { PORT_1A_INDEX, 1          , DISABLE    , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE  , VPP_PORT_0  , 0x4C           , NOT_HIDE},
+  { PORT_2A_INDEX, 7          , DISABLE    , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX, VPP_ADDR_MAX  , NOT_HIDE},
+  { PORT_3A_INDEX, 2          , DISABLE    , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE  , VPP_PORT_0   , 0x40         , ENABLE  , VPP_PORT_0  , 0x40         , NOT_HIDE},
+  { SOCKET_1_INDEX +
+    PORT_0_INDEX , NO_SLT_IMP , DISABLE    , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX, VPP_ADDR_MAX  , HIDE    },
+  // Slot 4 supports HP: PCA9554 (CPU1) Address 0x40, SCH (Rev 0.604) P 121 (MRL in J287)
+  { SOCKET_1_INDEX +
+    PORT_1A_INDEX, 4          , DISABLE    , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE  , VPP_PORT_1   , 0x40         , ENABLE  , VPP_PORT_0  , 0x40         , NOT_HIDE},
+  { SOCKET_1_INDEX +
+    PORT_1C_INDEX, 3          , DISABLE    , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE  , VPP_PORT_0  , 0x42         , NOT_HIDE},
+  { SOCKET_1_INDEX +
+    PORT_2A_INDEX, 6          , DISABLE    , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_1   , VPP_ADDR_MAX , ENABLE  , VPP_PORT_0  , 0x44         , NOT_HIDE},
+  { SOCKET_1_INDEX +
+    PORT_3A_INDEX, 5          , DISABLE    , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX, VPP_ADDR_MAX  , NOT_HIDE},
+};
+
+#endif //_IIOCFG_UPDATE_DXE_H_

+ 49 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf

@@ -0,0 +1,49 @@
+## @file
+#
+# @copyright
+# Copyright 2018 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = IioCfgUpdateDxeAowanda
+  FILE_GUID                      = 90171648-20AB-469E-A816-F46A2FC7447F
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = IioCfgUpdateEntry
+
+[Sources]
+  IioCfgUpdateDxe.c
+  IioCfgUpdateDxe.h
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  MemoryAllocationLib
+  DebugLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  UefiRuntimeServicesTableLib
+  UefiLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  WhitleySiliconPkg/WhitleySiliconPkg.dec
+  WhitleySiliconPkg/CpRcPkg.dec
+  WhitleySiliconPkg/SiliconPkg.dec
+  WhitleyOpenBoardPkg/PlatformPkg.dec
+
+[Guids]
+
+[FixedPcd]
+  gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
+
+[Protocols]
+  gUbaConfigDatabaseProtocolGuid
+
+[Depex]
+  gEfiPlatformTypeAowandaProtocolGuid

+ 112 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c

@@ -0,0 +1,112 @@
+/** @file
+  Slot Data Update.
+
+  @copyright
+  Copyright 2018 - 2021 Intel Corporation. <BR>
+  Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "SlotDataUpdateDxe.h"
+
+UINT8
+GetTypeAowandaIOU0Setting (
+  UINT8  IOU0Data
+)
+{
+  return IOU0Data;
+}
+
+UINT8
+GetTypeAowandaIOU2Setting (
+  UINT8  SkuPersonalityType,
+  UINT8  IOU2Data
+)
+{
+  return IOU2Data;
+}
+
+static IIO_BROADWAY_ADDRESS_DATA_ENTRY   SlotTypeAowandaBroadwayTable[] = {
+    {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 },
+    {Iio_Socket1, Iio_Iou1, Bw5_Addr_2},
+    {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 },
+};
+
+
+PLATFORM_SLOT_UPDATE_TABLE  TypeAowandaSlotTable =
+{
+  PLATFORM_SLOT_UPDATE_SIGNATURE,
+  PLATFORM_SLOT_UPDATE_VERSION,
+
+  SlotTypeAowandaBroadwayTable,
+  GetTypeAowandaIOU0Setting,
+  0
+};
+
+PLATFORM_SLOT_UPDATE_TABLE2  TypeAowandaSlotTable2 =
+{
+  PLATFORM_SLOT_UPDATE_SIGNATURE,
+  PLATFORM_SLOT_UPDATE_VERSION,
+
+  SlotTypeAowandaBroadwayTable,
+  GetTypeAowandaIOU0Setting,
+  0,
+  GetTypeAowandaIOU2Setting
+};
+
+/**
+  The Driver Entry Point.
+
+  The function is the driver Entry point.
+
+  @param ImageHandle   A handle for the image that is initializing this driver
+  @param SystemTable   A pointer to the EFI system table
+
+  @retval EFI_SUCCESS:              Driver initialized successfully
+  @retval EFI_LOAD_ERROR:           Failed to Initialize or has been loaded
+  @retval EFI_OUT_OF_RESOURCES      Could not allocate needed resources
+
+**/
+EFI_STATUS
+EFIAPI
+SlotDataUpdateEntry (
+  IN EFI_HANDLE                            ImageHandle,
+  IN EFI_SYSTEM_TABLE                      *SystemTable
+)
+{
+  EFI_STATUS                               Status;
+  UBA_CONFIG_DATABASE_PROTOCOL             *UbaConfigProtocol = NULL;
+
+  DEBUG((DEBUG_INFO, "UBA:SlotDataUpdate-TypeAowanda\n"));
+  Status = gBS->LocateProtocol (
+                  &gUbaConfigDatabaseProtocolGuid,
+                  NULL,
+                  &UbaConfigProtocol
+                  );
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  Status = UbaConfigProtocol->AddData (
+                                     UbaConfigProtocol,
+                                     &gPlatformSlotDataDxeGuid,
+                                     &TypeAowandaSlotTable,
+                                     sizeof(TypeAowandaSlotTable)
+                                     );
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  Status = UbaConfigProtocol->AddData (
+                                     UbaConfigProtocol,
+                                     &gPlatformSlotDataDxeGuid,
+                                     &TypeAowandaSlotTable2,
+                                     sizeof(TypeAowandaSlotTable2)
+                                     );
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  return Status;
+}

+ 57 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h

@@ -0,0 +1,57 @@
+/** @file
+
+  @copyright
+  Copyright 2016 - 2021 Intel Corporation. <BR>
+  Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SLOT_DATA_UPDATE_DXE_H_
+#define _SLOT_DATA_UPDATE_DXE_H_
+
+#include <Base.h>
+#include <Uefi.h>
+
+#include <Protocol/UbaCfgDb.h>
+
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PciLib.h>
+
+#include <Library/UbaSlotUpdateLib.h>
+#include <IioPlatformData.h>
+
+typedef enum {
+  Iio_Socket0 = 0,
+  Iio_Socket1,
+  Iio_Socket2,
+  Iio_Socket3,
+  Iio_Socket4,
+  Iio_Socket5,
+  Iio_Socket6,
+  Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+  Iio_Iou0 = 0,
+  Iio_Iou1,
+  Iio_Iou2,
+  Iio_Mcp0,
+  Iio_Mcp1,
+  Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+  Bw5_Addr_0 = 0,
+  Bw5_Addr_1,
+  Bw5_Addr_2,
+  Bw5_Addr_3,
+  Bw5_Addr_Max
+} BW5_ADDRESS;
+
+#endif //_SLOT_DATA_UPDATE_DXE_H_

+ 49 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf

@@ -0,0 +1,49 @@
+## @file
+#
+# @copyright
+# Copyright 2018 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SlotDataUpdateDxeAowanda
+  FILE_GUID                      = 5D22BB40-92CA-4A7C-93C5-9AEEC770A634
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = SlotDataUpdateEntry
+
+[Sources]
+  SlotDataUpdateDxe.c
+  SlotDataUpdateDxe.h
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  MemoryAllocationLib
+  DebugLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  UefiRuntimeServicesTableLib
+  UefiLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  WhitleySiliconPkg/WhitleySiliconPkg.dec
+  WhitleySiliconPkg/CpRcPkg.dec
+  WhitleySiliconPkg/SiliconPkg.dec
+  WhitleyOpenBoardPkg/PlatformPkg.dec
+
+[Guids]
+
+[FixedPcd]
+  gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
+
+[Protocols]
+  gUbaConfigDatabaseProtocolGuid
+
+[Depex]
+  gEfiPlatformTypeAowandaProtocolGuid

+ 128 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c

@@ -0,0 +1,128 @@
+/** @file
+
+  @copyright
+  Copyright 2018 - 2021 Intel Corporation. <BR>
+  Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "UsbOcUpdateDxe.h"
+
+#include <Library/UbaUsbOcUpdateLib.h>
+#include <PchLimits.h>
+#include <ConfigBlock/UsbConfig.h>
+#include <ConfigBlock/Usb2PhyConfig.h>
+
+USB_OVERCURRENT_PIN  TypeAowandaUsb20OverCurrentMappings[PCH_MAX_USB2_PORTS] = {
+  UsbOverCurrentPin0,                              // Port01: USB 2.0 CONNECTOR
+  UsbOverCurrentPinSkip,                           // Port02: NC
+  UsbOverCurrentPinSkip,                           // Port03: NC
+  UsbOverCurrentPinSkip,                           // Port04: NC
+  UsbOverCurrentPinSkip,                           // Port05: NC
+  UsbOverCurrentPinSkip,                           // Port06: NC
+  UsbOverCurrentPinSkip,                           // Port07: TO BMC
+  UsbOverCurrentPinSkip,                           // Port08: NC
+  UsbOverCurrentPinSkip,                           // Port09: NC
+  UsbOverCurrentPinSkip,                           // Port10: OCP3.0 SLOT
+  UsbOverCurrentPinSkip,                           // Port11: NC
+  UsbOverCurrentPinSkip,                           // Port12: NC
+  UsbOverCurrentPinSkip,                           // Port13: NC
+  UsbOverCurrentPinSkip,                           // Port14: NC
+  UsbOverCurrentPinSkip,                           // Port15: NC
+  UsbOverCurrentPinSkip                            // Port16: NC
+};
+
+USB_OVERCURRENT_PIN  TypeAowandaUsb30OverCurrentMappings[PCH_MAX_USB3_PORTS] = {
+  UsbOverCurrentPinSkip,                            // Port01: NC
+  UsbOverCurrentPinSkip,                            // Port02: NC
+  UsbOverCurrentPinSkip,                            // Port03: NC
+  UsbOverCurrentPinSkip,                            // Port04: NC
+  UsbOverCurrentPinSkip,                            // Port05: NC
+  UsbOverCurrentPinSkip,                            // Port06: NC
+  UsbOverCurrentPinSkip,                            // Port07: NC
+  UsbOverCurrentPinSkip,                            // Port08: NC
+  UsbOverCurrentPinSkip,                            // Port09: NC
+  UsbOverCurrentPinSkip                             // Port10: NC
+};
+
+USB2_PHY_PARAMETERS  TypeAowandaUsb20AfeParams[PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS] = {
+  { 3, 0, 3, 1 },                       // PP0
+  { 5, 0, 3, 1 },                       // PP1
+  { 3, 0, 3, 1 },                       // PP2
+  { 0, 5, 1, 1 },                       // PP3
+  { 3, 0, 3, 1 },                       // PP4
+  { 3, 0, 3, 1 },                       // PP5
+  { 3, 0, 3, 1 },                       // PP6
+  { 3, 0, 3, 1 },                       // PP7
+  { 2, 2, 1, 0 },                       // PP8
+  { 6, 0, 2, 1 },                       // PP9
+  { 2, 2, 1, 0 },                       // PP10
+  { 6, 0, 2, 1 },                       // PP11
+  { 0, 5, 1, 1 },                       // PP12
+  { 7, 0, 2, 1 },                       // PP13
+};
+
+EFI_STATUS
+TypeAowandaPlatformUsbOcUpdateCallback (
+  IN OUT   USB_OVERCURRENT_PIN  **Usb20OverCurrentMappings,
+  IN OUT   USB_OVERCURRENT_PIN  **Usb30OverCurrentMappings,
+  IN OUT   USB2_PHY_PARAMETERS  **Usb20AfeParams
+  )
+{
+  *Usb20OverCurrentMappings = &TypeAowandaUsb20OverCurrentMappings[0];
+  *Usb30OverCurrentMappings = &TypeAowandaUsb30OverCurrentMappings[0];
+
+  *Usb20AfeParams = TypeAowandaUsb20AfeParams;
+  return EFI_SUCCESS;
+}
+
+PLATFORM_USBOC_UPDATE_TABLE  TypeAowandaUsbOcUpdate =
+{
+  PLATFORM_USBOC_UPDATE_SIGNATURE,
+  PLATFORM_USBOC_UPDATE_VERSION,
+  TypeAowandaPlatformUsbOcUpdateCallback
+};
+
+/**
+  The Driver Entry Point.
+
+  The function is the driver Entry point.
+
+  @param ImageHandle   A handle for the image that is initializing this driver
+  @param SystemTable   A pointer to the EFI system table
+
+  @retval EFI_SUCCESS:              Driver initialized successfully
+  @retval EFI_LOAD_ERROR:           Failed to Initialize or has been loaded
+  @retval EFI_OUT_OF_RESOURCES      Could not allocate needed resources
+
+**/
+EFI_STATUS
+EFIAPI
+UsbOcUpdateEntry (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EFI_STATUS                    Status;
+  UBA_CONFIG_DATABASE_PROTOCOL  *UbaConfigProtocol = NULL;
+
+  DEBUG ((DEBUG_INFO, "UBA:UsbOcUpdate-TypeAowanda\n"));
+  Status = gBS->LocateProtocol (
+                  &gUbaConfigDatabaseProtocolGuid,
+                  NULL,
+                  &UbaConfigProtocol
+                  );
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  Status = UbaConfigProtocol->AddData (
+                                     UbaConfigProtocol,
+                                     &gDxePlatformUbaOcConfigDataGuid,
+                                     &TypeAowandaUsbOcUpdate,
+                                     sizeof(TypeAowandaUsbOcUpdate)
+                                     );
+
+  return Status;
+}

+ 24 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h

@@ -0,0 +1,24 @@
+/** @file
+
+  @copyright
+  Copyright 2015 - 2021 Intel Corporation. <BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _USBOC_UPDATE_DXE_H_
+#define _USBOC_UPDATE_DXE_H_
+
+#include <Base.h>
+#include <Uefi.h>
+
+#include <Protocol/UbaCfgDb.h>
+
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#endif //_USBOC_UPDATE_DXE_H_

+ 45 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf

@@ -0,0 +1,45 @@
+## @file
+#
+# @copyright
+# Copyright 2018 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = UsbOcUpdateDxeAowanda
+  FILE_GUID                      = 24CE8219-DBB5-4FA4-A2ED-DB87DA7EB6EB
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = UsbOcUpdateEntry
+
+[sources]
+  UsbOcUpdateDxe.c
+  UsbOcUpdateDxe.h
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  MemoryAllocationLib
+  DebugLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  UefiRuntimeServicesTableLib
+  UefiLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  WhitleySiliconPkg/WhitleySiliconPkg.dec
+  WhitleySiliconPkg/SiliconPkg.dec
+  WhitleyOpenBoardPkg/PlatformPkg.dec
+
+[Guids]
+
+[Protocols]
+  gUbaConfigDatabaseProtocolGuid
+
+[Depex]
+  gEfiPlatformTypeAowandaProtocolGuid

+ 54 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/AcpiTablePcds.c

@@ -0,0 +1,54 @@
+/** @file
+  ACPI table pcds update.
+
+  @copyright
+  Copyright 2015 - 2021 Intel Corporation. <BR>
+  Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/PcdLib.h>
+#include <Library/HobLib.h>
+#include <Guid/PlatformInfo.h>
+#include <UncoreCommonIncludes.h>
+#include <Cpu/CpuIds.h>
+
+EFI_STATUS
+TypeAowandaPlatformUpdateAcpiTablePcds (
+  VOID
+  )
+{
+  CHAR8  AcpiName10nm[]   = "EPRP10NM";         // USED for identify ACPI table for 10nm in systmeboard dxe driver
+  CHAR8  OemTableIdXhci[] = "xh_nccrb";
+
+  UINTN       Size;
+  EFI_STATUS  Status;
+
+  EFI_HOB_GUID_TYPE  *GuidHob;
+  EFI_PLATFORM_INFO  *PlatformInfo;
+
+  DEBUG ((DEBUG_INFO, "Uba Callback: PlatformAowandaUpdateAcpiTablePcds entered\n"));
+
+  GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+  ASSERT (GuidHob != NULL);
+  if (GuidHob == NULL) {
+    return EFI_NOT_FOUND;
+  }
+
+  PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
+  // #
+  // #ACPI items
+  // #
+  Size   = AsciiStrSize (AcpiName10nm);
+  Status = PcdSetPtrS (PcdOemSkuAcpiName, &Size, AcpiName10nm);
+  DEBUG ((DEBUG_INFO, "%a TypeAowanda ICX\n", __FUNCTION__));
+  ASSERT_EFI_ERROR (Status);
+
+  Size   = AsciiStrSize (OemTableIdXhci);
+  Status = PcdSetPtrS (PcdOemTableIdXhci, &Size, OemTableIdXhci);
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}

+ 329 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/GpioTable.c

@@ -0,0 +1,329 @@
+/** @file
+
+  @copyright
+  Copyright 2020 - 2021 Intel Corporation. <BR>
+  Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaGpioUpdateLib.h>
+
+#include <Library/GpioLib.h>
+#include <Library/UbaGpioInitLib.h>
+#include <GpioPinsSklH.h>
+#include <Library/PcdLib.h>
+
+//
+// Board     : Aowanda
+//
+static GPIO_INIT_CONFIG mGpioTableAowanda [] =
+  {
+// Group A AWD
+    {GPIO_SKL_H_GPP_A0,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_0_PU_IRQ_ESPI_ALERT1_N
+    {GPIO_SKL_H_GPP_A1,  { GpioPadModeNative3, GpioHostOwnDefault,    GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_1_ESPI_IO0
+    {GPIO_SKL_H_GPP_A2,  { GpioPadModeNative3, GpioHostOwnDefault,    GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_2_ESPI_IO1
+    {GPIO_SKL_H_GPP_A3,  { GpioPadModeNative3, GpioHostOwnDefault,    GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_3_ESPI_IO2
+    {GPIO_SKL_H_GPP_A4,  { GpioPadModeNative3, GpioHostOwnDefault,    GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_4_ESPI_IO3
+    {GPIO_SKL_H_GPP_A5,  { GpioPadModeNative3, GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_5_ESPI_CS0_N
+    {GPIO_SKL_H_GPP_A6,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_6_PU_ESPI_CS1_N
+    {GPIO_SKL_H_GPP_A7,  { GpioPadModeNative3, GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_7_IRQ_ESPI_ALERT0_N
+    {GPIO_SKL_H_GPP_A8,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_8_PU_LPC_CLKRUN_N
+    {GPIO_SKL_H_GPP_A9,  { GpioPadModeNative3, GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_9_ESPI_CLK
+    {GPIO_SKL_H_GPP_A10, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_10_TP_PCH_GPP_A10
+    {GPIO_SKL_H_GPP_A11, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_11_PU_LPC_PME_N
+    {GPIO_SKL_H_GPP_A12, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_12_PU_IRQ_PCH_SCI_WHEA_N
+    {GPIO_SKL_H_GPP_A13, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_13_TP_PCH_GPP_A13
+    {GPIO_SKL_H_GPP_A14, { GpioPadModeNative3, GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_14_RST_ESPI_RESET_N
+    {GPIO_SKL_H_GPP_A15, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_15_PU_SUSACK_N
+    {GPIO_SKL_H_GPP_A16, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_16_TP_PCH_GPP_A16
+    {GPIO_SKL_H_GPP_A17, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_17_TP_PCH_GPP_A17
+    {GPIO_SKL_H_GPP_A18, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_18_TP_PCH_GPP_A18
+    //ME recovery jumper
+    //{GPIO_SKL_H_GPP_A19, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_19_FM_ME_RCVR_N
+    {GPIO_SKL_H_GPP_A20, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_20_TP_PCH_GPP_A20
+    {GPIO_SKL_H_GPP_A21, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_21_TP_PCH_GPP_A21
+    {GPIO_SKL_H_GPP_A22, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_22_TP_PCH_GPP_A22
+    {GPIO_SKL_H_GPP_A23, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_23_TP_PCH_GPP_A23
+
+// Group B AWD
+    {GPIO_SKL_H_GPP_B0,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_0_FM_PCH_CORE_VID<0>
+    {GPIO_SKL_H_GPP_B1,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_1_FM_PCH_CORE_VID<1>
+    {GPIO_SKL_H_GPP_B2,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_2_PU_PCH_VRALERT_N
+    {GPIO_SKL_H_GPP_B3,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_3_FM_BIOS_ENTER_SETUP_N
+    {GPIO_SKL_H_GPP_B4,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_4_FM_BIOS_POST_START_N
+    {GPIO_SKL_H_GPP_B5,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_5_FM_OCP3_BIF_READY
+    {GPIO_SKL_H_GPP_B6,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_6_FM_CLKREQ_M2_SSD1_N
+    {GPIO_SKL_H_GPP_B7,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_7_FM_CLKREQ_M2_SSD2_N
+    {GPIO_SKL_H_GPP_B8,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_8_PU_GPP_PCH_B8
+    {GPIO_SKL_H_GPP_B9,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_9_FM_BOARD_REV_ID2
+    {GPIO_SKL_H_GPP_B10, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_10_FM_TPM_PRSNT_N
+    {GPIO_SKL_H_GPP_B11, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_11_FM_PMBUS_ALERT_BUF_EN_N
+    {GPIO_SKL_H_GPP_B12, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_12_TP_PCH_GPP_B12
+    {GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_13_RST_PLTRST_N
+    {GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_14_FM_PCH_BIOS_RCVR_SPKR
+    {GPIO_SKL_H_GPP_B15, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_15_FM_CPU_ERR0_PCH_N
+    {GPIO_SKL_H_GPP_B16, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_16_FM_CPU_ERR1_PCH_N
+    {GPIO_SKL_H_GPP_B17, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_17_FM_CPU_ERR2_PCH_N
+    {GPIO_SKL_H_GPP_B18, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_18_FM_NO_REBOOT
+    {GPIO_SKL_H_GPP_B19, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_19_FM_BOARD_SKU_ID5
+    {GPIO_SKL_H_GPP_B20, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_20_FM_BIOS_POST_CMPLT_N
+    {GPIO_SKL_H_GPP_B21, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_21_FM_FAST_PROCHOT_EN_N
+    {GPIO_SKL_H_GPP_B22, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_22_FM_OCP3_FRU
+    {GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_23_FM_PCH_BMC_THRMTRIP_EXI_STRAP_N
+
+// Group C AWD
+    {GPIO_SKL_H_GPP_C0,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_0_SMB4_HOST_STBY_BMC_LVC3_SCL
+    {GPIO_SKL_H_GPP_C1,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_1_SMB4_HOST_STBY_BMC_LVC3_SDA
+    {GPIO_SKL_H_GPP_C2,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_2_PU_PCH_TLS_ENABLE_STRAP_PCH
+    {GPIO_SKL_H_GPP_C3,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_3_SMB6_SMLINK0_STBY_LVC3_SCL
+    {GPIO_SKL_H_GPP_C4,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_4_SMB6_SMLINK0_STBY_LVC3_SDA
+    {GPIO_SKL_H_GPP_C5,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_5_IRQ_SML0_ALERT_N
+    {GPIO_SKL_H_GPP_C6,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_6_SMB8_PMBUS_SML1_STBY_LVC3_SCL
+    {GPIO_SKL_H_GPP_C7,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_7_SMB8_PMBUS_SML1_STBY_LVC3_SDA
+    {GPIO_SKL_H_GPP_C8,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_8_FM_PASSWORD_CLEAR_N
+    {GPIO_SKL_H_GPP_C9,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_9_FM_MFG_MODE
+    {GPIO_SKL_H_GPP_C10, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_10_FM_SATA_RAID_KEY
+    {GPIO_SKL_H_GPP_C11, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_11_TP_PCH_GPP_C11
+    {GPIO_SKL_H_GPP_C12, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_12_FM_BOARD_REV_ID0
+    {GPIO_SKL_H_GPP_C13, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_13_FM_BOARD_REV_ID1
+    {GPIO_SKL_H_GPP_C14, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_14_FM_BMC_PCH_SCI_LPC_N
+    {GPIO_SKL_H_GPP_C15, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_15_FM_RISER1_ID_0
+    {GPIO_SKL_H_GPP_C16, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_16_FM_RISER1_ID_1
+    {GPIO_SKL_H_GPP_C17, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_17_FM_RISER1_ID_2
+    {GPIO_SKL_H_GPP_C18, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_18_FM_RISER2_ID_0
+    {GPIO_SKL_H_GPP_C19, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_19_FM_RISER2_ID_1
+    // ME PROCHOT
+    //{GPIO_SKL_H_GPP_C20, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_20_FM_THROTTLE_N
+    {GPIO_SKL_H_GPP_C21, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_21_RST_PCH_PCIE_SMB_MUX_NX1
+    {GPIO_SKL_H_GPP_C22, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_22_IRQ_BMC_PCH_SMI_LPC_N
+    {GPIO_SKL_H_GPP_C23, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_23_FM_CPU_CATERR_DLY_LVT3_R_N
+
+// Group D AWD
+    {GPIO_SKL_H_GPP_D0,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntLevel | GpioIntNmi, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_0_IRQ_BMC_PCH_NMI
+    {GPIO_SKL_H_GPP_D1,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_1_TP_PCH_GPP_D1
+    {GPIO_SKL_H_GPP_D2,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_2_TP_PCH_GPP_D2
+    {GPIO_SKL_H_GPP_D3,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_3_TP_PCH_GPP_D3
+    {GPIO_SKL_H_GPP_D4,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_4_FM_PLD_PCH_DATA
+    {GPIO_SKL_H_GPP_D5,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_5_FM_OCP3_BIF0
+    {GPIO_SKL_H_GPP_D6,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_6_FM_OCP3_BIF1
+    {GPIO_SKL_H_GPP_D7,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_7_FM_OCP3_BIF2
+    {GPIO_SKL_H_GPP_D8,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_8_TP_PCH_GPP_D8
+    {GPIO_SKL_H_GPP_D9,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_9_IRQ_FORCE_NM_THROTTLE_N
+    {GPIO_SKL_H_GPP_D10, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_10_TP_PCH_GPP_D10
+    {GPIO_SKL_H_GPP_D11, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_11_IRQ_LOM_ALERT_N
+    {GPIO_SKL_H_GPP_D12, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_12_PU_PCH_GPP_D12
+    {GPIO_SKL_H_GPP_D13, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_13_PU_PCH_GPP_D13
+    {GPIO_SKL_H_GPP_D14, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_14_PU_PCH_GPP_D14
+    {GPIO_SKL_H_GPP_D15, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_15_PU_PCH_GPP_D15
+    {GPIO_SKL_H_GPP_D16, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_16_FM_ME_PFR_1
+    {GPIO_SKL_H_GPP_D17, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_17_FM_ME_PFR_2
+    {GPIO_SKL_H_GPP_D18, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_18_PU_PCH_GPP_D18
+    {GPIO_SKL_H_GPP_D19, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_19_FM_PS_PWROK_DLY_SEL_R
+    {GPIO_SKL_H_GPP_D20, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_20_FM_OCP3_PRSNTB0_N
+    {GPIO_SKL_H_GPP_D21, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_21_FM_OCP3_PRSNTB1_N
+    {GPIO_SKL_H_GPP_D22, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_22_FM_OCP3_PRSNTB2_N
+    {GPIO_SKL_H_GPP_D23, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_23_FM_OCP3_PRSNTB3_N
+
+// Group E AWD
+    {GPIO_SKL_H_GPP_E0,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_0_FM_M2_SSD1_PEDET
+    // ME Heartbeat
+    //{GPIO_SKL_H_GPP_E1,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_1_FM_ME_HEARTBEAT_N
+    {GPIO_SKL_H_GPP_E2,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_2_TP_PCH_GPP_E2
+    {GPIO_SKL_H_GPP_E3,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_3_FM_ADR_TRIGGER_R_N
+    {GPIO_SKL_H_GPP_E4,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_4_FM_HSC_TIMER_EXP_N
+    {GPIO_SKL_H_GPP_E5,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_5_TP_PCH_GPP_E5
+    {GPIO_SKL_H_GPP_E6,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_6_TP_PCH_GPP_E6
+    {GPIO_SKL_H_GPP_E7,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_7_FM_ADR_SMI_GPIO_R_N
+    {GPIO_SKL_H_GPP_E8,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_8_TP_PCH_GPP_E8
+    {GPIO_SKL_H_GPP_E9,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_9_OC_PCH_USB_P01_N
+    {GPIO_SKL_H_GPP_E10, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_10_TP_PCH_GPP_E10
+    {GPIO_SKL_H_GPP_E11, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_11_PU_PCH_GPP_E11
+    {GPIO_SKL_H_GPP_E12, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_12_IRQ_UV_DETECT_N
+
+// Group F AWD
+    {GPIO_SKL_H_GPP_F0,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_0_IRQ_OC_DETECT_N
+    {GPIO_SKL_H_GPP_F1,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_1_FM_M2_SSD2_PEDET
+    {GPIO_SKL_H_GPP_F2,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_2_FM_PCIE_SLOT1_PRSNT_N
+    {GPIO_SKL_H_GPP_F3,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_3_FM_PCIE_SLOT2_PRSNT_N
+    {GPIO_SKL_H_GPP_F4,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_4_FM_PCIE_SLOT3_PRSNT_N
+    {GPIO_SKL_H_GPP_F5,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_5_IRQ_TPM_SPI_N
+    {GPIO_SKL_H_GPP_F6,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_6_FM_EDSFF0_PRSNT_N
+    {GPIO_SKL_H_GPP_F7,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_7_FM_EDSFF1_PRSNT_N
+    {GPIO_SKL_H_GPP_F8,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_8_FM_EDSFF2_PRSNT_N
+    {GPIO_SKL_H_GPP_F9,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_9_FM_EDSFF3_PRSNT_N
+    {GPIO_SKL_H_GPP_F10, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_10_PU_PCH_GPP_F10
+    {GPIO_SKL_H_GPP_F11, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_11_PU_PCH_GPP_F11
+    {GPIO_SKL_H_GPP_F12, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_12_PU_PCH_GPP_F12
+    {GPIO_SKL_H_GPP_F13, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_13_PU_PCH_GPP_F13
+    {GPIO_SKL_H_GPP_F14, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_14_PU_PCH_GPP_F14
+    {GPIO_SKL_H_GPP_F15, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_15_FM_FORCE_ADR_N
+    {GPIO_SKL_H_GPP_F16, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_16_PU_PCH_GPP_F16
+    {GPIO_SKL_H_GPP_F17, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_17_PU_PCH_GPP_F17
+    {GPIO_SKL_H_GPP_F18, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_18_PU_PCH_GPP_F18
+    {GPIO_SKL_H_GPP_F19, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_19_PU_PCH_GPP_F19
+    {GPIO_SKL_H_GPP_F20, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_20_PU_PCH_GPP_F20
+    {GPIO_SKL_H_GPP_F21, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_21_PU_PCH_GPP_F21
+    {GPIO_SKL_H_GPP_F22, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_22_PU_PCH_GPP_F22
+    {GPIO_SKL_H_GPP_F23, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_23_PU_PCH_GPP_F23
+
+// Group G AWD
+    {GPIO_SKL_H_GPP_G0,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_0_TP_PCH_GPP_G0
+    {GPIO_SKL_H_GPP_G1,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_1_TP_PCH_GPP_G1
+    {GPIO_SKL_H_GPP_G2,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_2_TP_PCH_GPP_G2
+    {GPIO_SKL_H_GPP_G3,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_3_TP_PCH_GPP_G3
+    {GPIO_SKL_H_GPP_G4,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_4_TP_PCH_GPP_G4
+    {GPIO_SKL_H_GPP_G5,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_5_TP_PCH_GPP_G5
+    {GPIO_SKL_H_GPP_G6,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_6_TP_PCH_GPP_G6
+    {GPIO_SKL_H_GPP_G7,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_7_TP_PCH_GPP_G7
+    {GPIO_SKL_H_GPP_G8,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_8_TP_PCH_GPP_G8
+    {GPIO_SKL_H_GPP_G9,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_9_TP_PCH_GPP_G9
+    {GPIO_SKL_H_GPP_G10, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_10_TP_PCH_GPP_G10
+    {GPIO_SKL_H_GPP_G11, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_11_TP_PCH_GPP_G11
+    {GPIO_SKL_H_GPP_G12, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_12_FM_BOARD_SKU_ID0
+    {GPIO_SKL_H_GPP_G13, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_13_FM_BOARD_SKU_ID1
+    {GPIO_SKL_H_GPP_G14, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_14_FM_BOARD_SKU_ID2
+    {GPIO_SKL_H_GPP_G15, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_15_FM_BOARD_SKU_ID3
+    {GPIO_SKL_H_GPP_G16, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_16_FM_BOARD_SKU_ID4
+    {GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_17_FM_ADR_COMPLETE
+    {GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_18_IRQ_NMI_EVENT_N
+    {GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_19_IRQ_SMI_ACTIVE_N
+    {GPIO_SKL_H_GPP_G20, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_20_IRQ_SML1_PMBUS_PCH_ALERT_N
+    {GPIO_SKL_H_GPP_G21, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_21_PU_PCH_GPP_G21
+    {GPIO_SKL_H_GPP_G22, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_22_TP_PCH_GPP_G22
+    {GPIO_SKL_H_GPP_G23, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_23_TP_PCH_GPP_G23
+
+// Group H AWD
+    {GPIO_SKL_H_GPP_H0,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_0_TP_PCH_GPP_H0
+    {GPIO_SKL_H_GPP_H1,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_1_TP_PCH_GPP_H1
+    {GPIO_SKL_H_GPP_H2,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_2_TP_PCH_GPP_H2
+    {GPIO_SKL_H_GPP_H3,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_3_M2_SSD1_PRSNT_N
+    {GPIO_SKL_H_GPP_H4,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_4_M2_SSD2_PRSNT_N
+    {GPIO_SKL_H_GPP_H5,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_5_FM_OCP3_CLK0_EN_R_N
+    {GPIO_SKL_H_GPP_H6,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_6_FM_OCP3_CLK1_EN_R_N
+    {GPIO_SKL_H_GPP_H7,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_7_FM_OCP3_CLK2_EN_R_N
+    {GPIO_SKL_H_GPP_H8,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_8_FM_OCP3_CLK3_EN_R_N
+    {GPIO_SKL_H_GPP_H9,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_9_TP_PCH_GPP_H9
+    {GPIO_SKL_H_GPP_H10, { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_10_SMB11_SMLINK2_STBY_LVC3_SCL
+    {GPIO_SKL_H_GPP_H11, { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_11_SMB11_SMLINK2_STBY_LVC3_SDA
+    {GPIO_SKL_H_GPP_H12, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_12_FM_ESPI_FLASH_MODE
+    {GPIO_SKL_H_GPP_H13, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_13_PU_PCH_GPP_H13
+    {GPIO_SKL_H_GPP_H14, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_14_PU_PCH_GPP_H14
+    {GPIO_SKL_H_GPP_H15, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_15_PU_ADR_TIMER_HOLD_OFF_N
+    {GPIO_SKL_H_GPP_H16, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_16_PU_PCH_GPP_H16
+    {GPIO_SKL_H_GPP_H17, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_17_PU_PCH_GPP_H17
+    {GPIO_SKL_H_GPP_H18, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_18_FM_LT_KEY_DOWNGRADE_N
+    {GPIO_SKL_H_GPP_H19, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_19_TP_PCH_GPP_H19
+    {GPIO_SKL_H_GPP_H20, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_20_TP_PCH_GPP_H20
+    {GPIO_SKL_H_GPP_H21, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_21_TP_PCH_GPP_H21
+    {GPIO_SKL_H_GPP_H22, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_22_TP_PCH_GPP_H22
+    {GPIO_SKL_H_GPP_H23, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_23_TP_PCH_GPP_H23
+
+// Group I AWD
+    {GPIO_SKL_H_GPP_I0,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_0_TP_PCH_GPP_I0
+    {GPIO_SKL_H_GPP_I1,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_1_TP_PCH_GPP_I1
+    {GPIO_SKL_H_GPP_I2,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_2_TP_PCH_GPP_I2
+    {GPIO_SKL_H_GPP_I3,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_3_TP_PCH_GPP_I3
+    {GPIO_SKL_H_GPP_I4,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_4_TP_PCH_GPP_I4
+    {GPIO_SKL_H_GPP_I5,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_5_TP_PCH_GPP_I5
+    {GPIO_SKL_H_GPP_I6,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_6_TP_PCH_GPP_I6
+    {GPIO_SKL_H_GPP_I7,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_7_TP_PCH_GPP_I7
+    {GPIO_SKL_H_GPP_I8,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_8_TP_PCH_GPP_I8
+    {GPIO_SKL_H_GPP_I9,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_9_TP_PCH_GPP_I9
+    {GPIO_SKL_H_GPP_I10, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_10_TP_PCH_GPP_I10
+//    {GPIO_SKL_H_GPP_I11, { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_11_PD_3P3_RCOMP
+
+// Group GPD AWD
+    {GPIO_SKL_H_GPD0,    { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_0_FM_FIVRBREAK_N
+    {GPIO_SKL_H_GPD1,    { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_1_PU_ACPRESENT_PCH
+    {GPIO_SKL_H_GPD2,    { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_2_IRQ_HSC_FAULT_N
+    {GPIO_SKL_H_GPD3,    { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_3_FM_PCH_PWRBTN_N
+    {GPIO_SKL_H_GPD4,    { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_4_FM_SLPS3_N
+    {GPIO_SKL_H_GPD5,    { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_5_FM_SLPS4_N
+    {GPIO_SKL_H_GPD6,    { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_6_TP_SLPA_N
+    {GPIO_SKL_H_GPD7,    { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_7_TP_GPD_7
+    {GPIO_SKL_H_GPD8,    { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_8_TP_CLK_33K_PCH_SUSCLK
+    {GPIO_SKL_H_GPD9,    { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_9_TP_GPD_9
+    {GPIO_SKL_H_GPD10,   { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_10_TP_SLPS5_N
+    //{GPIO_SKL_H_GPD10,   { GpioPadModeGpio,    GpioHostOwnGpio,     GpioDirIn,    GpioOutDefault, GpioIntDis, GpioResetPwrGood,    GpioTermNone,    GpioPadConfigLock}},//GPD_10_TP_GPD_10_SLPS5_N
+    {GPIO_SKL_H_GPD11,   { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_11_FM_GBE_LOM_DISABLE_N
+
+// Group J AWD
+    {GPIO_SKL_H_GPP_J0,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_0_TP_GPP_J_IO<0>
+    {GPIO_SKL_H_GPP_J1,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_1_TP_GPP_J_IO<1>
+    {GPIO_SKL_H_GPP_J2,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_2_TP_GPP_J_IO<2>
+    {GPIO_SKL_H_GPP_J3,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_3_TP_GPP_J_IO<3>
+    {GPIO_SKL_H_GPP_J4,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_4_TP_GPP_J_IO<4>
+    {GPIO_SKL_H_GPP_J5,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_5_TP_GPP_J_IO<5>
+    {GPIO_SKL_H_GPP_J6,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_6_TP_GPP_J_IO<6>
+    {GPIO_SKL_H_GPP_J7,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_7_TP_GPP_J_IO<7>
+    {GPIO_SKL_H_GPP_J8,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_8_TP_GPP_J_IO<8>
+    {GPIO_SKL_H_GPP_J9,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_9_TP_GPP_J_IO<9>
+    {GPIO_SKL_H_GPP_J10, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_10_TP_GPP_J_IO<10>
+    {GPIO_SKL_H_GPP_J11, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_11_TP_GPP_J_IO<11>
+    {GPIO_SKL_H_GPP_J12, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_12_TP_GPP_J_IO<12>
+    {GPIO_SKL_H_GPP_J13, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_13_TP_GPP_J_IO<13>
+    {GPIO_SKL_H_GPP_J14, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_14_TP_GPP_J_IO<14>
+    {GPIO_SKL_H_GPP_J15, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_15_TP_GPP_J_IO<15>
+    {GPIO_SKL_H_GPP_J16, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_16_TP_GPP_J_IO<16>
+    {GPIO_SKL_H_GPP_J17, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_17_TP_GPP_J_IO<17>
+    {GPIO_SKL_H_GPP_J18, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_18_TP_GPP_J_IO<18>
+    {GPIO_SKL_H_GPP_J19, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_19_TP_GPP_J_IO<19>
+    {GPIO_SKL_H_GPP_J20, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_20_TP_GPP_J_IO<20>
+    {GPIO_SKL_H_GPP_J21, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_21_TP_GPP_J_IO<21>
+    {GPIO_SKL_H_GPP_J22, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_22_TP_GPP_J_IO<22>
+    {GPIO_SKL_H_GPP_J23, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_23_TP_GPP_J_IO<23>
+
+// Group K AWD
+    {GPIO_SKL_H_GPP_K0,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_0_TP_PCH_GPP_K0
+    {GPIO_SKL_H_GPP_K1,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_1_TP_PCH_GPP_K1
+    {GPIO_SKL_H_GPP_K2,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_2_TP_PCH_GPP_K2
+    {GPIO_SKL_H_GPP_K3,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_3_TP_PCH_GPP_K3
+    {GPIO_SKL_H_GPP_K4,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_4_TP_PCH_GPP_K4
+    {GPIO_SKL_H_GPP_K5,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_5_TP_PCH_GPP_K5
+    {GPIO_SKL_H_GPP_K6,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_6_TP_PCH_GPP_K6
+    {GPIO_SKL_H_GPP_K7,  { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_7_FM_PCH_GBE_DEBUG_EN
+    {GPIO_SKL_H_GPP_K8,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_8_PD_RMII_PCH_CONN_ARB_IN
+    {GPIO_SKL_H_GPP_K9,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,      GpioOutHigh,    GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_9_PD_RMII_PCH_ARB_OUT
+    {GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_10_RST_PCIE_PCH_PERST_N
+//    {GPIO_SKL_H_GPP_K11, { GpioPadModeNative1, GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_11_PD_1P8_3P3_RCOMP
+
+// Group L AWD
+    {GPIO_SKL_H_GPP_L2,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,       GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_2_TP_GPP_L_IO<2>
+    {GPIO_SKL_H_GPP_L3,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,       GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_3_TP_GPP_L_IO<3>
+    {GPIO_SKL_H_GPP_L4,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,       GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_4_TP_GPP_L_IO<4>
+    {GPIO_SKL_H_GPP_L5,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,       GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_5_TP_GPP_L_IO<5>
+    {GPIO_SKL_H_GPP_L6,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,       GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_6_TP_GPP_L_IO<6>
+    {GPIO_SKL_H_GPP_L7,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,       GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_7_TP_GPP_L_IO<7>
+    {GPIO_SKL_H_GPP_L8,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,       GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_8_TP_GPP_L_IO<8>
+    {GPIO_SKL_H_GPP_L9,  { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,       GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_9_TP_GPP_L_IO<9>
+    {GPIO_SKL_H_GPP_L10, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,       GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_10_TP_GPP_L_IO<10>
+    {GPIO_SKL_H_GPP_L11, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,       GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_11_TP_GPP_L_IO<11>
+    {GPIO_SKL_H_GPP_L12, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,       GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_12_TP_GPP_L_IO<12>
+    {GPIO_SKL_H_GPP_L13, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,       GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_13_TP_GPP_L_IO<13>
+    {GPIO_SKL_H_GPP_L14, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,       GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_14_TP_GPP_L_IO<14>
+    {GPIO_SKL_H_GPP_L15, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,       GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_15_TP_GPP_L_IO<15>
+    {GPIO_SKL_H_GPP_L16, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,       GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_16_TP_GPP_L_IO<16>
+    {GPIO_SKL_H_GPP_L17, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,       GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_17_TP_GPP_L_IO<17>
+    {GPIO_SKL_H_GPP_L18, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,       GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_18_TP_GPP_L_IO<18>
+    {GPIO_SKL_H_GPP_L19, { GpioPadModeGpio,    GpioHostOwnDefault,    GpioDirOut,       GpioOutHigh,     GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_19_TP_GPP_L_IO<19>
+};
+
+EFI_STATUS
+TypeAowandaInstallGpioData (
+  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
+)
+{
+  EFI_STATUS                            Status;
+
+  Status = UbaConfigPpi->AddData (
+                                 UbaConfigPpi,
+                                 &gPlatformGpioInitDataGuid,
+                                 &mGpioTableAowanda,
+                                 sizeof(mGpioTableAowanda)
+                                 );
+  Status = PcdSet32S (PcdOemSku_GPIO_TABLE_SIZE, sizeof (mGpioTableAowanda));
+  ASSERT_EFI_ERROR (Status);
+  return Status;
+}

+ 186 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/IioBifurInit.c

@@ -0,0 +1,186 @@
+/** @file
+  IIO Config Update.
+
+  @copyright
+  Copyright 2018 - 2021 Intel Corporation. <BR>
+  Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaIioConfigLib.h>
+#include <IioPlatformData.h>
+
+typedef enum {
+  Iio_Socket0 = 0,
+  Iio_Socket1,
+  Iio_Socket2,
+  Iio_Socket3,
+  Iio_Socket4,
+  Iio_Socket5,
+  Iio_Socket6,
+  Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+  Iio_Iou0 = 0,
+  Iio_Iou1,
+  Iio_Iou2,
+  Iio_Iou3,
+  Iio_Iou4,
+  Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+  VPP_PORT_0 = 0,
+  VPP_PORT_1,
+  VPP_PORT_2,
+  VPP_PORT_3
+} VPP_PORT;
+
+#define ENABLE   1
+#define DISABLE  0
+
+#define SPLS_1X  0
+
+static IIO_BIFURCATION_DATA_ENTRY_EX  IioBifurcationTable[] =
+{
+  { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX  },
+  { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX  },
+  { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX  },
+  { Iio_Socket0, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX  },
+  { Iio_Socket0, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX  }
+};
+
+static IIO_SLOT_CONFIG_DATA_ENTRY_EX  IioSlotTable[] = {
+  // Port Index  | Slot       |Interlock |power       |Power        |Hotplug  |Vpp Port      |Vpp Addr      |PCIeSSD  |PCIeSSD       |PCIeSSD       |Hidden    |Common   |  SRIS   |Uplink   |Retimer  |Retimer       |Retimer       |Retimer    |Mux           |Mux           |ExtnCard |ExtnCard      |ExtnCard      |ExtnCard |ExtnCard Retimer|ExtnCard Retimer|ExtnCard |ExtnCard Hotplug|ExtnCard Hotplug|Max Retimer|
+  //             |            |          |Limit Scale |Limit Value  |Cap      |              |              |Cap      |Port          |Address       |          |Clock    |         |Port     |         |Address       |Channel       |Width      |Address       |Channel       |Support  |SMBus Port    |SMBus Addr    |Retimer  |SMBus Address   |Width           |Hotplug  |Vpp Port        |Vpp Address     |           |
+  {SOCKET_0_INDEX +
+    PORT_1A_INDEX, 1          , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
+
+  {SOCKET_0_INDEX +
+    PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
+
+  {SOCKET_0_INDEX +
+    PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
+
+   {SOCKET_0_INDEX +
+    PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
+
+  {SOCKET_0_INDEX +
+    PORT_2A_INDEX, 2          , DISABLE ,     SPLS_1X ,          25 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
+  {SOCKET_0_INDEX +
+    PORT_2B_INDEX, NO_SLT_IMP , DISABLE ,     SPLS_1X ,          25 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
+  {SOCKET_0_INDEX +
+    PORT_2C_INDEX, NO_SLT_IMP , DISABLE ,     SPLS_1X ,          25 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
+  {SOCKET_0_INDEX +
+    PORT_2D_INDEX, NO_SLT_IMP , DISABLE ,     SPLS_1X ,          25 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
+
+  {SOCKET_0_INDEX +
+    PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
+  {SOCKET_0_INDEX +
+    PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
+  {SOCKET_0_INDEX +
+    PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
+   {SOCKET_0_INDEX +
+    PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
+
+  {SOCKET_0_INDEX +
+    PORT_4A_INDEX, 0x30       , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE  , VPP_PORT_0   , 0x40         , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
+  {SOCKET_0_INDEX +
+    PORT_4B_INDEX, 0x31       , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE  , VPP_PORT_1   , 0x40         , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
+  {SOCKET_0_INDEX +
+    PORT_4C_INDEX, 0x32       , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE  , VPP_PORT_0   , 0x42         , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
+  {SOCKET_0_INDEX +
+    PORT_4D_INDEX, 0x33       , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE  , VPP_PORT_1   , 0x42         , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
+
+  {SOCKET_0_INDEX +
+    PORT_5A_INDEX, 4          , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , ENABLE  , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
+  {SOCKET_0_INDEX +
+    PORT_5B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , ENABLE  , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
+  {SOCKET_0_INDEX +
+    PORT_5C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , ENABLE  , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
+  {SOCKET_0_INDEX +
+    PORT_5D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , ENABLE  , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      }
+
+};
+
+EFI_STATUS
+UpdateAowandaIioConfig (
+  IN  IIO_GLOBALS  *IioGlobalData
+  )
+{
+  return EFI_SUCCESS;
+}
+
+PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX  TypeAowandaIioConfigTable =
+{
+  PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE,
+  PLATFORM_IIO_CONFIG_UPDATE_VERSION_2,
+
+  IioBifurcationTable,
+  sizeof (IioBifurcationTable),
+  UpdateAowandaIioConfig,
+  IioSlotTable,
+  sizeof (IioSlotTable)
+};
+
+/**
+  Entry point function for the PEIM
+
+  @param FileHandle      Handle of the file being invoked.
+  @param PeiServices     Describes the list of possible PEI Services.
+
+  @return EFI_SUCCESS    If we installed our PPI
+
+**/
+EFI_STATUS
+TypeAowandaIioPortBifurcationInit (
+  IN UBA_CONFIG_DATABASE_PPI  *UbaConfigPpi
+  )
+{
+  EFI_STATUS  Status;
+
+  Status = UbaConfigPpi->AddData (
+                                  UbaConfigPpi,
+                                  &gPlatformIioConfigDataGuid,
+                                  &TypeAowandaIioConfigTable,
+                                  sizeof (TypeAowandaIioConfigTable)
+                                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = UbaConfigPpi->AddData (
+                                  UbaConfigPpi,
+                                  &gPlatformIioConfigDataGuid_1,
+                                  &TypeAowandaIioConfigTable,
+                                  sizeof (TypeAowandaIioConfigTable)
+                                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = UbaConfigPpi->AddData (
+                                  UbaConfigPpi,
+                                  &gPlatformIioConfigDataGuid_2,
+                                  &TypeAowandaIioConfigTable,
+                                  sizeof (TypeAowandaIioConfigTable)
+                                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = UbaConfigPpi->AddData (
+                                  UbaConfigPpi,
+                                  &gPlatformIioConfigDataGuid_3,
+                                  &TypeAowandaIioConfigTable,
+                                  sizeof (TypeAowandaIioConfigTable)
+                                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  return Status;
+}

+ 86 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/KtiEparam.c

@@ -0,0 +1,86 @@
+/** @file
+
+  @copyright
+  Copyright 2018 - 2021 Intel Corporation. <BR>
+  Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <KtiSetupDefinitions.h>
+#include <UbaKti.h>
+#include <UncoreCommonIncludes.h>
+
+extern EFI_GUID  gPlatformKtiEparamUpdateDataGuid;
+
+ALL_LANES_EPARAM_LINK_INFO  KtiAowandaAllLanesEparamTable[] = {
+  //
+  // SocketID, Freq, Link, TXEQL, CTLEPEAK
+  // Please propagate changes to WilsonCitySMT and WilsonCityModular UBA KtiEparam tables
+  //
+  //
+  // Socket 0
+  //
+  { 0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK0), 0x2B33373F, ADAPTIVE_CTLE },
+  { 0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK1), 0x2A33363F, ADAPTIVE_CTLE },
+  { 0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK2), 0x2B34363F, ADAPTIVE_CTLE }
+};
+
+PLATFORM_KTI_EPARAM_UPDATE_TABLE  TypeAowandaKtiEparamUpdate =
+{
+  PLATFORM_KTIEP_UPDATE_SIGNATURE,
+  PLATFORM_KTIEP_UPDATE_VERSION,
+  KtiAowandaAllLanesEparamTable,
+  sizeof (KtiAowandaAllLanesEparamTable),
+  NULL,
+  0
+};
+
+ALL_LANES_EPARAM_LINK_INFO  KtiAowandaCpxAllLanesEparamTable[] = {
+  //
+  // SocketID, Freq, Link, TXEQL, CTLEPEAK
+  //
+  //
+  // Socket 0
+  //
+  { 0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK0), 0x2E39343F, ADAPTIVE_CTLE },
+  { 0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK5), 0x2F39353F, ADAPTIVE_CTLE }
+};
+
+PLATFORM_KTI_EPARAM_UPDATE_TABLE  TypeAowandaCpxKtiEparamUpdate =
+{
+  PLATFORM_KTIEP_UPDATE_SIGNATURE,
+  PLATFORM_KTIEP_UPDATE_VERSION,
+  KtiAowandaCpxAllLanesEparamTable,
+  sizeof (KtiAowandaCpxAllLanesEparamTable),
+  NULL,
+  0
+};
+
+EFI_STATUS
+TypeAowandaInstallKtiEparamData (
+  IN UBA_CONFIG_DATABASE_PPI  *UbaConfigPpi
+  )
+{
+  EFI_STATUS         Status;
+  EFI_HOB_GUID_TYPE  *GuidHob;
+  EFI_PLATFORM_INFO  *PlatformInfo;
+
+  GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+  ASSERT (GuidHob != NULL);
+  if (GuidHob == NULL) {
+    return EFI_NOT_FOUND;
+  }
+
+  PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
+
+  Status = UbaConfigPpi->AddData (
+                                  UbaConfigPpi,
+                                  &gPlatformKtiEparamUpdateDataGuid,
+                                  &TypeAowandaKtiEparamUpdate,
+                                  sizeof (TypeAowandaKtiEparamUpdate)
+                                  );
+
+  return Status;
+}

+ 381 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PcdData.c

@@ -0,0 +1,381 @@
+/** @file
+
+  @copyright
+  Copyright 2018 - 2021 Intel Corporation. <BR>
+  Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <ImonVrSvid.h>
+#include <Library/MemVrSvidMapLib.h>
+#include <Guid/PlatformInfo.h>
+#include <Library/UbaPcdUpdateLib.h>
+#include <Library/PcdLib.h>
+#include <UncoreCommonIncludes.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+#include <CpuAndRevisionDefines.h>
+
+#include <Library/PchMultiPch.h>
+#include <GpioInitData.h>
+#include <Library/GpioLib.h>
+
+
+#define BIOSGUARD_SUPPORT_ENABLED BIT0
+#define GPIO_SKL_H_GPP_B20        0x01010014
+#define PCIE_RISER 0x1A
+#define EDSFF_RISER 0x4A
+
+static GPIO_PAD mEDSFFRiserId [] = {
+  GPIO_SKL_H_GPP_C18,
+  GPIO_SKL_H_GPP_C19
+};
+
+static GPIO_PAD mPCIeRiserId [] = {
+  GPIO_SKL_H_GPP_C15,
+  GPIO_SKL_H_GPP_C16,
+  GPIO_SKL_H_GPP_C17
+};
+
+const UINT8 EDSFFRiserIdGpioPadsNum = sizeof(mEDSFFRiserId)/sizeof(GPIO_PAD);
+const UINT8 PCIeRiserIdGpioPadsNum = sizeof(mPCIeRiserId)/sizeof(GPIO_PAD);
+
+static EFI_STATUS
+GpioGetRiserId (
+  IN UINT8  Type,
+  OUT UINT32 *RiserId
+  )
+{
+  EFI_STATUS              Status;
+  UINT32                  Data32;
+  UINT8                   i;
+  UINT32                  RevId = 0;
+  DYNAMIC_SI_LIBARY_PPI  *DynamicSiLibraryPpi;
+
+  Status = EFI_DEVICE_ERROR;
+  RevId = 0;
+  DynamicSiLibraryPpi = NULL;
+
+  DEBUG((EFI_D_INFO, "%a Entry...\n", __FUNCTION__));
+
+  Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+  if (EFI_ERROR (Status)) {
+    ASSERT_EFI_ERROR (Status);
+    return Status;
+  }
+
+  if (Type == EDSFF_RISER) {
+    //
+    //Get EDSFF GPIO Present Ping
+    //
+    for (i = 0; i < EDSFFRiserIdGpioPadsNum; i++){
+      Status = DynamicSiLibraryPpi->GpioGetInputValueByPchId (PCH_LEGACY_ID, mEDSFFRiserId[i], &Data32);
+      DEBUG((EFI_D_INFO,"GpioGetInputValueByPchId[%x] mEDSFFRiserId Status = %r\n", i, Status));
+      if (EFI_ERROR(Status)) {
+        return Status;
+      }
+      if (Data32) {
+        RevId = RevId | (1 << i);
+      }
+    }
+  } else if (Type == PCIE_RISER) {
+    //
+    //Get PCIe Riser GPIO Present Ping
+    //
+    for (i = 0; i < PCIeRiserIdGpioPadsNum; i++){
+      Status = DynamicSiLibraryPpi->GpioGetInputValueByPchId (PCH_LEGACY_ID, mPCIeRiserId[i], &Data32);
+      DEBUG((EFI_D_INFO,"GpioGetInputValueByPchId[%x] PCIe Riser Status = %r\n", i, Status));
+      if (EFI_ERROR(Status)) {
+        return Status;
+      }
+      if (Data32) {
+        RevId = RevId | (1 << i);
+      }
+    }
+  }
+  *RiserId = RevId;
+  return EFI_SUCCESS;
+}
+
+/**
+  Update Aowanda IMON SVID Information
+
+  retval N/A
+**/
+VOID
+TypeAowandaPlatformUpdateImonAddress (
+  VOID
+  )
+{
+  VCC_IMON *VccImon = NULL;
+  UINTN Size = 0;
+
+  Size = sizeof (VCC_IMON);
+  VccImon = (VCC_IMON *) PcdGetPtr (PcdImonAddr);
+  if (VccImon == NULL) {
+    DEBUG ((DEBUG_ERROR, "UpdateImonAddress() - PcdImonAddr == NULL\n"));
+    return;
+  }
+
+  VccImon->VrSvid[0] = PcdGet8 (PcdWilsonCitySvidVrP1V8);
+  VccImon->VrSvid[1] = PcdGet8 (PcdWilsonCitySvidVrVccAna);
+  VccImon->VrSvid[2] = IMON_ADDR_LIST_END; // End array with 0xFF
+
+  PcdSetPtrS (PcdImonAddr, &Size, (VOID *) VccImon);
+}
+
+/**
+  Update Aowanda VR ID SVID Information
+
+  retval N/A
+**/
+VOID
+TypeAowandaPlatformUpdateVrIdAddress (
+  VOID
+  )
+{
+  MEM_SVID_MAP *MemSvidMap = NULL;
+  UINTN Size = 0;
+
+  Size = sizeof (MEM_SVID_MAP);
+  MemSvidMap = (MEM_SVID_MAP *) PcdGetPtr (PcdMemSrvidMap);
+  if (MemSvidMap == NULL) {
+    DEBUG ((DEBUG_ERROR, "UpdateVrIdAddress() - PcdMemSrvidMap == NULL\n"));
+    return;
+  }
+  /*
+    Map VR ID Address to Memory controller
+    The mailbox command can support up to 4 DDR VR ID's, 0x10, 0x12, 0x14, and 0x16.
+    Whitley PHAS indicates that Whitley (like Purley) only connects 2 VRs (VR ID's 0x10 and 0x12).
+    Those are typically shared such that MC0/MC2 share the same DDR VR (as they are on the same side of the CPU)
+    and MC1/MC3 share the other. Depending on motherboard layout and other design constraints, this could change
+    BIT   4 => 0 or 1, SVID BUS\Interface 0 or 1 respectively
+    BIT 0:3 => SVID ADDRESS
+  */
+
+  MemSvidMap->Socket[0].Mc[0] = 0x10;  //SVID BUS 1, ADDR 0
+  MemSvidMap->Socket[0].Mc[1] = 0x12;  //SVID BUS 1, ADDR 2
+  MemSvidMap->Socket[1].Mc[0] = 0x10;  //SVID BUS 1, ADDR 0
+  MemSvidMap->Socket[1].Mc[1] = 0x12;  //SVID BUS 1, ADDR 2
+  MemSvidMap->Socket[2].Mc[0] = 0x10;  //SVID BUS 1, ADDR 0
+  MemSvidMap->Socket[2].Mc[1] = 0x12;  //SVID BUS 1, ADDR 2
+  MemSvidMap->Socket[3].Mc[0] = 0x10;  //SVID BUS 1, ADDR 0
+  MemSvidMap->Socket[3].Mc[1] = 0x12;  //SVID BUS 1, ADDR 2
+  MemSvidMap->Socket[4].Mc[0] = 0x10;  //SVID BUS 1, ADDR 0
+  MemSvidMap->Socket[4].Mc[1] = 0x12;  //SVID BUS 1, ADDR 2
+  MemSvidMap->Socket[5].Mc[0] = 0x10;  //SVID BUS 1, ADDR 0
+  MemSvidMap->Socket[5].Mc[1] = 0x12;  //SVID BUS 1, ADDR 2
+  MemSvidMap->Socket[6].Mc[0] = 0x10;  //SVID BUS 1, ADDR 0
+  MemSvidMap->Socket[6].Mc[1] = 0x12;  //SVID BUS 1, ADDR 2
+  MemSvidMap->Socket[7].Mc[0] = 0x10;  //SVID BUS 1, ADDR 0
+  MemSvidMap->Socket[7].Mc[1] = 0x12;  //SVID BUS 1, ADDR 2
+
+  PcdSetPtrS (PcdMemSrvidMap, &Size, (VOID *) MemSvidMap);
+}
+
+EFI_STATUS
+TypeAowandaPlatformPcdUpdateCallback (
+  VOID
+)
+{
+  CHAR8     FamilyName[]  = "Whitley";
+
+  CHAR8     BoardName[]   = "Aowanda";
+  UINT32    Data32;
+  UINTN     Size;
+  UINTN     PlatformFeatureFlag = 0;
+
+  UINT32    PCIE_RiserID;
+  UINT32    EDSFF_RiserID;
+
+  CHAR16    PlatformName[]   = L"AD1S02";
+  UINTN     PlatformNameSize = 0;
+  EFI_STATUS Status;
+
+  //#Integer for BoardID, must match the SKU number and be unique.
+  Status = PcdSet16S (PcdOemSkuBoardID, TypeAowanda);
+  ASSERT_EFI_ERROR(Status);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+  Status = PcdSet16S (PcdOemSkuBoardFamily, 0x30);
+  ASSERT_EFI_ERROR(Status);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  // Number of Sockets on Board.
+  Status = PcdSet32S (PcdOemSkuBoardSocketCount, 1);
+  ASSERT_EFI_ERROR(Status);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  // Max channel and max DIMM
+  Status = PcdSet32S (PcdOemSkuMaxChannel , 8);
+  ASSERT_EFI_ERROR(Status);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+  Status = PcdSet32S (PcdOemSkuMaxDimmPerChannel , 1);
+  ASSERT_EFI_ERROR(Status);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+  Status = PcdSetBoolS (PcdOemSkuDimmLayout, TRUE);
+  ASSERT_EFI_ERROR(Status);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  //Update Onboard Video Controller PCI Ven_id, Dev_id
+  Status = PcdSet16S (PcdOnboardVideoPciVendorId, 0x1A03);
+  ASSERT_EFI_ERROR(Status);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  Status = PcdSet16S (PcdOnboardVideoPciDeviceId, 0x2000);
+  ASSERT_EFI_ERROR(Status);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  //#
+  //# Misc.
+  //#
+  //# V_PCIE_PORT_PXPSLOTCTRL_ATNLED_OFF
+  Status = PcdSet16S (PcdOemSkuMrlAttnLed, 0xc0);
+  ASSERT_EFI_ERROR(Status);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  //SDP Active Flag
+  Status = PcdSet8S (PcdOemSkuSdpActiveFlag , 0x0);
+  ASSERT_EFI_ERROR(Status);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  //# Zero terminated string to ID family
+  Size = AsciiStrSize (FamilyName);
+  Status = PcdSetPtrS (PcdOemSkuFamilyName, &Size, FamilyName);
+  ASSERT_EFI_ERROR(Status);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  //# Zero terminated string to Board Name
+  Size = AsciiStrSize (BoardName);
+  Status = PcdSetPtrS (PcdOemSkuBoardName, &Size, BoardName);
+  ASSERT_EFI_ERROR(Status);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+//
+// Detect riser id to distinguish the SKU
+//
+
+  GpioGetRiserId (PCIE_RISER, &PCIE_RiserID);
+  GpioGetRiserId (EDSFF_RISER, &EDSFF_RiserID);
+  switch(PCIE_RiserID) {
+    case 0:
+      switch (EDSFF_RiserID) {
+        case 0:
+          StrCpyS (PlatformName, sizeof (PlatformName) / sizeof (CHAR16), L"AD1S01");
+          break;
+        case 2://1RU RISER2(AD1S02)
+          StrCpyS (PlatformName, sizeof (PlatformName) / sizeof (CHAR16), L"AD1S02");
+          break;
+        default:
+          StrCpyS (PlatformName, sizeof (PlatformName) / sizeof (CHAR16), L"AD1S01");
+          break;
+      }
+      break;
+    default:
+      StrCpyS (PlatformName, sizeof (PlatformName) / sizeof (CHAR16), L"AD1S01");
+      break;
+  }
+
+  PlatformNameSize = sizeof (PlatformName);
+  Status = PcdSet32S (PcdOemSkuPlatformNameSize, (UINT32)PlatformNameSize);
+  ASSERT_EFI_ERROR(Status);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+  Status = PcdSetPtrS (PcdOemSkuPlatformName, &PlatformNameSize, PlatformName);
+  ASSERT_EFI_ERROR(Status);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  //# FeaturesBasedOnPlatform
+  Status = PcdSet32S (PcdOemSkuPlatformFeatureFlag, (UINT32)PlatformFeatureFlag);
+  ASSERT_EFI_ERROR(Status);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  //# Assert GPIO
+  Data32 = 0;
+  Status = PcdSet32S (PcdOemSkuAssertPostGPIOValue, Data32);
+  ASSERT_EFI_ERROR(Status);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+  Status = PcdSet32S (PcdOemSkuAssertPostGPIO, GPIO_SKL_H_GPP_B20);
+  ASSERT_EFI_ERROR(Status);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  //# UplinkPortIndex
+  Status = PcdSet8S (PcdOemSkuUplinkPortIndex, 5);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  DEBUG ((DEBUG_INFO, "Uba Callback: PlatformPcdUpdateCallback is called!\n"));
+  Status = TypeAowandaPlatformUpdateAcpiTablePcds ();
+  //# BMC Pcie Port Number
+  // PCH PCIe port 3 is used for BMC VGA.
+  //
+  PcdSet8S (PcdOemSkuBmcPciePortNumber, 3);
+
+  ASSERT_EFI_ERROR(Status);
+
+  //# Board Type Bit Mask
+  PcdSet32S (PcdBoardTypeBitmask, CPU_TYPE_F_MASK | (CPU_TYPE_F_MASK << 4));
+  ASSERT_EFI_ERROR(Status);
+
+  //Update IMON Address
+  TypeAowandaPlatformUpdateImonAddress ();
+
+  return Status;
+}
+
+PLATFORM_PCD_UPDATE_TABLE    TypeAowandaPcdUpdateTable =
+{
+  PLATFORM_PCD_UPDATE_SIGNATURE,
+  PLATFORM_PCD_UPDATE_VERSION,
+  TypeAowandaPlatformPcdUpdateCallback
+};
+
+EFI_STATUS
+TypeAowandaInstallPcdData (
+  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
+)
+{
+  EFI_STATUS                            Status;
+
+  Status = UbaConfigPpi->AddData (
+                                 UbaConfigPpi,
+                                 &gPlatformPcdConfigDataGuid,
+                                 &TypeAowandaPcdUpdateTable,
+                                 sizeof(TypeAowandaPcdUpdateTable)
+                                 );
+
+  return Status;
+}

+ 82 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PchEarlyUpdate.c

@@ -0,0 +1,82 @@
+/** @file
+  Pch Early update.
+
+  @copyright
+  Copyright 2019 - 2021 Intel Corporation. <BR>
+  Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+
+#include <Library/UbaPchEarlyUpdateLib.h>
+
+#include <PchAccess.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioLib.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+
+EFI_STATUS
+TypeAowandaPchLanConfig (
+  IN SYSTEM_CONFIGURATION         *SystemConfig
+)
+{
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+TypeAowandaOemInitLateHook (
+  IN SYSTEM_CONFIGURATION         *SystemConfig
+)
+{
+  return EFI_SUCCESS;
+}
+
+
+PLATFORM_PCH_EARLY_UPDATE_TABLE  TypeAowandaPchEarlyUpdateTable =
+{
+  PLATFORM_PCH_EARLY_UPDATE_SIGNATURE,
+  PLATFORM_PCH_EARLY_UPDATE_VERSION,
+  TypeAowandaPchLanConfig,
+  TypeAowandaOemInitLateHook
+};
+
+
+/**
+  Entry point function for the PEIM
+
+  @param FileHandle      Handle of the file being invoked.
+  @param PeiServices     Describes the list of possible PEI Services.
+
+  @return EFI_SUCCESS    If we installed our PPI
+
+**/
+EFI_STATUS
+EFIAPI
+TypeAowandaPchEarlyUpdate(
+  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
+  )
+{
+  EFI_STATUS                            Status;
+
+  Status = PeiServicesLocatePpi (
+             &gUbaConfigDatabasePpiGuid,
+             0,
+             NULL,
+             &UbaConfigPpi
+             );
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  Status = UbaConfigPpi->AddData (
+                               UbaConfigPpi,
+                               &gPlatformPchEarlyConfigDataGuid,
+                               &TypeAowandaPchEarlyUpdateTable,
+                               sizeof(TypeAowandaPchEarlyUpdateTable)
+                               );
+
+  return Status;
+}

+ 77 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PeiBoardInit.h

@@ -0,0 +1,77 @@
+/** @file
+  PeiBoardInit.
+
+  @copyright
+  Copyright 2018 - 2021 Intel Corporation. <BR>
+  Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_BOARD_INIT_PEIM_H_
+#define _PEI_BOARD_INIT_PEIM_H_
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Ppi/UbaCfgDb.h>
+#include <Guid/PlatformInfo.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/HobLib.h>
+#include <MemCommon.h>
+#include <Cpu/CpuIds.h>
+
+// TypeAowanda
+EFI_STATUS
+TypeAowandaPlatformUpdateUsbOcMappings (
+  IN UBA_CONFIG_DATABASE_PPI  *UbaConfigPpi
+  );
+
+EFI_STATUS
+TypeAowandaPlatformUpdateAcpiTablePcds (
+  VOID
+  );
+
+EFI_STATUS
+TypeAowandaInstallClockgenData (
+  IN UBA_CONFIG_DATABASE_PPI  *UbaConfigPpi
+  );
+
+EFI_STATUS
+TypeAowandaInstallPcdData (
+  IN UBA_CONFIG_DATABASE_PPI  *UbaConfigPpi
+  );
+
+EFI_STATUS
+TypeAowandaPchEarlyUpdate (
+  IN UBA_CONFIG_DATABASE_PPI  *UbaConfigPpi
+  );
+
+EFI_STATUS
+TypeAowandaIioPortBifurcationInit (
+  IN UBA_CONFIG_DATABASE_PPI  *UbaConfigPpi
+  );
+
+EFI_STATUS
+TypeAowandaInstallSlotTableData (
+  IN UBA_CONFIG_DATABASE_PPI  *UbaConfigPpi
+  );
+
+EFI_STATUS
+TypeAowandaInstallKtiEparamData (
+  IN UBA_CONFIG_DATABASE_PPI  *UbaConfigPpi
+  );
+
+// TypeAowanda
+EFI_STATUS
+TypeAowandaInstallGpioData (
+  IN UBA_CONFIG_DATABASE_PPI  *UbaConfigPpi
+  );
+
+EFI_STATUS
+TypeAowandaInstallSoftStrapData (
+  IN UBA_CONFIG_DATABASE_PPI  *UbaConfigPpi
+  );
+
+#endif // _PEI_BOARD_INIT_PEIM_H_

+ 154 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PeiBoardInitLib.c

@@ -0,0 +1,154 @@
+/** @file
+
+ @copyright
+  Copyright 2018 - 2021 Intel Corporation.
+  Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+/**
+  The constructor function for Board Init Libray.
+
+  @param  FileHandle  Handle of the file being invoked.
+  @param  PeiServices Describes the list of possible PEI Services.
+
+  @retval  EFI_SUCCESS            Table initialization successfully.
+  @retval  EFI_OUT_OF_RESOURCES   No enough memory to initialize table.
+**/
+
+#include "PeiBoardInit.h"
+#include <UncoreCommonIncludes.h>
+
+EFI_STATUS
+EFIAPI
+TypeAowandaPeiBoardInitLibConstructor (
+  IN EFI_PEI_FILE_HANDLE     FileHandle,
+  IN CONST EFI_PEI_SERVICES  **PeiServices
+  )
+{
+  EFI_STATUS               Status = EFI_SUCCESS;
+  UBA_CONFIG_DATABASE_PPI  *UbaConfigPpi;
+  EFI_HOB_GUID_TYPE        *GuidHob;
+  EFI_PLATFORM_INFO        *PlatformInfo;
+  UINT8                    SocketIndex;
+  UINT8                    ChannelIndex;
+
+  GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+  ASSERT (GuidHob != NULL);
+  if (GuidHob == NULL) {
+    return EFI_NOT_FOUND;
+  }
+
+  PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
+
+  if (PlatformInfo->BoardId == TypeAowanda) {
+    DEBUG ((DEBUG_INFO, "PEI UBA init BoardId 0x%X: TypeAowanda\n", PlatformInfo->BoardId));
+
+    // Socket 0 has SMT DIMM connector, Socket 1 has PTH DIMM connector
+    for (SocketIndex = 0; SocketIndex < MAX_SOCKET; SocketIndex++) {
+      for (ChannelIndex = 0; ChannelIndex < MAX_CH; ChannelIndex++) {
+        switch (SocketIndex) {
+          case 0:
+            PlatformInfo->MemoryConnectorType[SocketIndex][ChannelIndex] = DimmConnectorSmt;
+            break;
+          case 1:
+          // Fall through since socket 1 is PTH type
+          default:
+            // Use the more restrictive type as the default case
+            PlatformInfo->MemoryConnectorType[SocketIndex][ChannelIndex] = DimmConnectorPth;
+            break;
+        }
+      }
+    }
+
+    BuildGuidDataHob (
+      &gEfiPlatformInfoGuid,
+      &(PlatformInfo),
+      sizeof (EFI_PLATFORM_INFO)
+      );
+
+    Status = PeiServicesLocatePpi (
+               &gUbaConfigDatabasePpiGuid,
+               0,
+               NULL,
+               &UbaConfigPpi
+               );
+    if (EFI_ERROR(Status)) {
+      return Status;
+    }
+
+    Status = UbaConfigPpi->InitSku (
+                       UbaConfigPpi,
+                       PlatformInfo->BoardId,
+                       NULL,
+                       NULL
+                       );
+    ASSERT_EFI_ERROR (Status);
+
+    Status = TypeAowandaInstallGpioData (UbaConfigPpi);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+
+    Status = TypeAowandaInstallPcdData (UbaConfigPpi);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+
+    Status = TypeAowandaInstallSoftStrapData (UbaConfigPpi);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+
+    Status = TypeAowandaPchEarlyUpdate (UbaConfigPpi);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+
+    Status = TypeAowandaPlatformUpdateUsbOcMappings (UbaConfigPpi);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+
+    Status = TypeAowandaInstallSlotTableData (UbaConfigPpi);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+
+    Status = TypeAowandaInstallKtiEparamData (UbaConfigPpi);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+
+    for (SocketIndex = 0; SocketIndex < MAX_SOCKET; SocketIndex++) {
+      //
+      // Set default memory type connector.
+      // Socket 0: DimmConnectorSmt
+      // Socket 1: DimmConnectorPth
+      //
+      if (SocketIndex % 2 == 0) {
+        (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType[SocketIndex], sizeof (PlatformInfo->MemoryConnectorType[SocketIndex]), DimmConnectorSmt);
+      } else {
+        (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType[SocketIndex], sizeof (PlatformInfo->MemoryConnectorType[SocketIndex]), DimmConnectorPth);
+      }
+    }
+
+    //
+    // Initialize InterposerType to InterposerUnknown
+    //
+    for (SocketIndex = 0; SocketIndex < MAX_SOCKET; ++SocketIndex) {
+      PlatformInfo->InterposerType[SocketIndex] = InterposerUnknown;
+    }
+
+    //
+    //  TypeAowandaIioPortBifurcationInit will use PlatformInfo->InterposerType for PPO.
+    //
+    Status = TypeAowandaIioPortBifurcationInit (UbaConfigPpi);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+  }
+
+  return Status;
+}

+ 167 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PeiBoardInitLib.inf

@@ -0,0 +1,167 @@
+## @file
+# Component information file for BoardInitLib in PEI post memory phase.
+#
+# @copyright
+#  Copyright 2018 - 2021 Intel Corporation.
+#  Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+# @par Specification Reference:
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = TypeAowandaPeiBoardInitLib
+  FILE_GUID                      = 60EDF2C0-42D1-4868-A038-9CC7F2CD0E59
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = NULL|PEIM
+  CONSTRUCTOR                    = TypeAowandaPeiBoardInitLibConstructor
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  BaseMemoryLib
+  MemoryAllocationLib
+  PeiServicesLib
+  HobLib
+  PeiServicesTablePointerLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  WhitleySiliconPkg/WhitleySiliconPkg.dec
+  WhitleyOpenBoardPkg/PlatformPkg.dec
+  WhitleySiliconPkg/SiliconPkg.dec
+  WhitleySiliconPkg/CpRcPkg.dec
+
+[Sources]
+  PeiBoardInitLib.c
+  GpioTable.c
+  PcdData.c
+  UsbOC.c
+  AcpiTablePcds.c
+  IioBifurInit.c
+  SlotTable.c
+  KtiEparam.c
+  PchEarlyUpdate.c
+  SoftStrapFixup.c
+  PeiBoardInit.h
+
+[FixedPcd]
+
+[Pcd]
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+  gOemSkuTokenSpaceGuid.PcdOemSkuBoardID
+  gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID
+  gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily
+
+  gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName
+  gOemSkuTokenSpaceGuid.PcdOemSkuBoardName
+
+  gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount
+
+  gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel
+  gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel
+  gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout
+
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13
+
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13
+
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04
+  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05
+
+  gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName
+
+  gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed
+  gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag
+
+  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL
+  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL
+  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL
+  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL
+  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL
+  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL
+  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL
+  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL
+  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL
+  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL
+  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL
+  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE
+
+  gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32
+
+  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00
+  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01
+  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02
+  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03
+  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04
+  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05
+  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06
+  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07
+  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08
+  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09
+  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10
+  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11
+
+  gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName
+  gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize
+  gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag
+  gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO
+  gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue
+  gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber
+  gOemSkuTokenSpaceGuid.PcdOemTableIdXhci
+  gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex
+  gPlatformTokenSpaceGuid.PcdBoardTypeBitmask
+  gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrP1V8
+  gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrVccAna
+  gEfiCpRcPkgTokenSpaceGuid.PcdImonAddr
+  gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidMap
+
+  gPlatformTokenSpaceGuid.PcdMemInterposerMap
+  gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId
+  gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId
+
+[Ppis]
+  gUbaConfigDatabasePpiGuid
+  gDynamicSiLibraryPpiGuid                  ## CONSUMES
+
+[Guids]
+  gPlatformGpioInitDataGuid
+
+[Depex]
+  gDynamicSiLibraryPpiGuid

+ 167 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/SlotTable.c

@@ -0,0 +1,167 @@
+/** @file
+  Slot Table Update.
+
+  @copyright
+  Copyright 2018 - 2021 Intel Corporation. <BR>
+  Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaSlotUpdateLib.h>
+#include <IioPlatformData.h>
+
+#define PCI_DEVICE_ON_BOARD_TRUE   0
+#define PCI_DEVICE_ON_BOARD_FALSE  1
+
+typedef enum {
+  Iio_Socket0 = 0,
+  Iio_Socket1,
+  Iio_Socket2,
+  Iio_Socket3,
+  Iio_Socket4,
+  Iio_Socket5,
+  Iio_Socket6,
+  Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+  Iio_Iou0 = 0,
+  Iio_Iou1,
+  Iio_Iou2,
+  Iio_Iou3,
+  Iio_Iou4,
+  Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+  Bw5_Addr_0 = 0,
+  Bw5_Addr_1,
+  Bw5_Addr_2,
+  Bw5_Addr_3,
+  Bw5_Addr_Max
+} BW5_ADDRESS;
+
+static UINT8  TypeAowandaPchPciSlotImpementedTableData[] = {
+  PCI_DEVICE_ON_BOARD_TRUE,     // Root Port 0 I210
+  PCI_DEVICE_ON_BOARD_FALSE,    // Root Port 1
+  PCI_DEVICE_ON_BOARD_FALSE,    // Root Port 2
+  PCI_DEVICE_ON_BOARD_TRUE,     // Root Port 3 BMC Video
+  PCI_DEVICE_ON_BOARD_FALSE,    // Root Port 4
+  PCI_DEVICE_ON_BOARD_FALSE,    // Root Port 5
+  PCI_DEVICE_ON_BOARD_FALSE,    // Root Port 6
+  PCI_DEVICE_ON_BOARD_FALSE,    // Root Port 7
+  PCI_DEVICE_ON_BOARD_FALSE,    // Root Port 8
+  PCI_DEVICE_ON_BOARD_FALSE,    // Root Port 9
+  PCI_DEVICE_ON_BOARD_FALSE,    // Root Port 10
+  PCI_DEVICE_ON_BOARD_FALSE,    // Root Port 11
+  PCI_DEVICE_ON_BOARD_FALSE,    // Root Port 12
+  PCI_DEVICE_ON_BOARD_FALSE,    // Root Port 13
+  PCI_DEVICE_ON_BOARD_FALSE,    // Root Port 14
+  PCI_DEVICE_ON_BOARD_FALSE,    // Root Port 15
+  PCI_DEVICE_ON_BOARD_FALSE,    // Root Port 16
+  PCI_DEVICE_ON_BOARD_FALSE,    // Root Port 17
+  PCI_DEVICE_ON_BOARD_FALSE,    // Root Port 18
+  PCI_DEVICE_ON_BOARD_FALSE     // Root Port 19
+};
+
+UINT8
+GetTypeAowandaIOU0Setting (
+  UINT8  IOU0Data
+  )
+{
+  return IOU0Data;
+}
+
+UINT8
+GetTypeAowandaIOU2Setting (
+  UINT8  SkuPersonalityType,
+  UINT8  IOU2Data
+  )
+{
+  return IOU2Data;
+}
+
+static IIO_BROADWAY_ADDRESS_DATA_ENTRY  SlotTypeAowandaBroadwayTable[] = {
+  { Iio_Socket0, Iio_Iou2, Bw5_Addr_0 },
+  { Iio_Socket1, Iio_Iou1, Bw5_Addr_2 },
+  { Iio_Socket1, Iio_Iou0, Bw5_Addr_1 },
+};
+
+PLATFORM_SLOT_UPDATE_TABLE  TypeAowandaSlotTable =
+{
+  PLATFORM_SLOT_UPDATE_SIGNATURE,
+  PLATFORM_SLOT_UPDATE_VERSION,
+
+  SlotTypeAowandaBroadwayTable,
+  GetTypeAowandaIOU0Setting,
+  0
+};
+
+PLATFORM_SLOT_UPDATE_TABLE2  TypeAowandaSlotTable2 =
+{
+  PLATFORM_SLOT_UPDATE_SIGNATURE,
+  PLATFORM_SLOT_UPDATE_VERSION,
+
+  SlotTypeAowandaBroadwayTable,
+  GetTypeAowandaIOU0Setting,
+  0,
+  GetTypeAowandaIOU2Setting
+};
+
+PLATFORM_PCH_PCI_SLOT_IMPLEMENTED_UPDATE_TABLE  TypeAowandaPchPciSlotImplementedTable = {
+  PLATFORM_SLOT_UPDATE_SIGNATURE,
+  PLATFORM_SLOT_UPDATE_VERSION,
+
+  TypeAowandaPchPciSlotImpementedTableData
+};
+
+/**
+  Entry point function for the PEIM
+
+  @param FileHandle      Handle of the file being invoked.
+  @param PeiServices     Describes the list of possible PEI Services.
+
+  @return EFI_SUCCESS    If we installed our PPI
+
+**/
+EFI_STATUS
+TypeAowandaInstallSlotTableData (
+  IN UBA_CONFIG_DATABASE_PPI  *UbaConfigPpi
+  )
+{
+  EFI_STATUS  Status;
+
+  Status = UbaConfigPpi->AddData (
+                                  UbaConfigPpi,
+                                  &gPlatformSlotDataGuid,
+                                  &TypeAowandaSlotTable,
+                                  sizeof (TypeAowandaSlotTable)
+                                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = UbaConfigPpi->AddData (
+                                  UbaConfigPpi,
+                                  &gPlatformSlotDataGuid2,
+                                  &TypeAowandaSlotTable2,
+                                  sizeof (TypeAowandaSlotTable2)
+                                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = UbaConfigPpi->AddData (
+                                  UbaConfigPpi,
+                                  &gPlatformPciSlotImplementedGuid,
+                                  &TypeAowandaPchPciSlotImplementedTable,
+                                  sizeof (TypeAowandaPchPciSlotImplementedTable)
+                                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  return Status;
+}

+ 73 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/SoftStrapFixup.c

@@ -0,0 +1,73 @@
+/** @file
+  Soft Strap update.
+
+  @copyright
+  Copyright 2018 - 2021 Intel Corporation. <BR>
+  Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaSoftStrapUpdateLib.h>
+#include <GpioConfig.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioLib.h>
+#include <Library/HobLib.h>
+#include <Guid/PlatformInfo.h>
+
+PLATFORM_PCH_SOFTSTRAP_FIXUP_ENTRY  TypeAowandaSoftStrapTable[] =
+{
+  // SoftStrapNumber, LowBit, BitLength, Value
+  { 0, 0, 0, 0 }
+};
+
+UINT32
+TypeAowandaSystemBoardRevIdValue (
+  VOID
+  )
+{
+  EFI_HOB_GUID_TYPE  *GuidHob;
+  EFI_PLATFORM_INFO  *PlatformInfo;
+
+  GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+  ASSERT (GuidHob != NULL);
+  if (GuidHob == NULL) {
+    return 0xFF;
+  }
+
+  PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
+  return PlatformInfo->TypeRevisionId;
+}
+
+VOID
+TypeAowandaPlatformSpecificUpdate (
+  IN OUT  UINT8  *FlashDescriptorCopy
+  )
+{
+}
+
+PLATFORM_PCH_SOFTSTRAP_UPDATE  TypeAowandaSoftStrapUpdate =
+{
+  PLATFORM_SOFT_STRAP_UPDATE_SIGNATURE,
+  PLATFORM_SOFT_STRAP_UPDATE_VERSION,
+  TypeAowandaSoftStrapTable,
+  TypeAowandaPlatformSpecificUpdate
+};
+
+EFI_STATUS
+TypeAowandaInstallSoftStrapData (
+  IN UBA_CONFIG_DATABASE_PPI  *UbaConfigPpi
+  )
+{
+  EFI_STATUS  Status;
+
+  Status = UbaConfigPpi->AddData (
+                                  UbaConfigPpi,
+                                  &gPlatformPchSoftStrapConfigDataGuid,
+                                  &TypeAowandaSoftStrapUpdate,
+                                  sizeof (TypeAowandaSoftStrapUpdate)
+                                  );
+
+  return Status;
+}

+ 124 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/UsbOC.c

@@ -0,0 +1,124 @@
+/** @file
+
+  @copyright
+  Copyright 2018 - 2021 Intel Corporation. <BR>
+  Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+
+#include <Library/PcdLib.h>
+#include <Library/UbaUsbOcUpdateLib.h>
+#include <PchLimits.h>
+#include <ConfigBlock/UsbConfig.h>
+#include <ConfigBlock/Usb2PhyConfig.h>
+
+USB_OVERCURRENT_PIN  TypeAowandaUsb20OverCurrentMappings[PCH_MAX_USB2_PORTS] = {
+  UsbOverCurrentPin0,                              // Port01: USB 2.0 CONNECTOR
+  UsbOverCurrentPinSkip,                           // Port02: NC
+  UsbOverCurrentPinSkip,                           // Port03: NC
+  UsbOverCurrentPinSkip,                           // Port04: NC
+  UsbOverCurrentPinSkip,                           // Port05: NC
+  UsbOverCurrentPinSkip,                           // Port06: NC
+  UsbOverCurrentPinSkip,                           // Port07: TO BMC
+  UsbOverCurrentPinSkip,                           // Port08: NC
+  UsbOverCurrentPinSkip,                           // Port09: NC
+  UsbOverCurrentPinSkip,                           // Port10: OCP3.0 SLOT
+  UsbOverCurrentPinSkip,                           // Port11: NC
+  UsbOverCurrentPinSkip,                           // Port12: NC
+  UsbOverCurrentPinSkip,                           // Port13: NC
+  UsbOverCurrentPinSkip,                           // Port14: NC
+  UsbOverCurrentPinSkip,                           // Port15: NC
+  UsbOverCurrentPinSkip                            // Port16: NC
+};
+
+USB_OVERCURRENT_PIN  TypeAowandaUsb30OverCurrentMappings[PCH_MAX_USB3_PORTS] = {
+  UsbOverCurrentPinSkip,                            // Port01: NC
+  UsbOverCurrentPinSkip,                            // Port02: NC
+  UsbOverCurrentPinSkip,                            // Port03: NC
+  UsbOverCurrentPinSkip,                            // Port04: NC
+  UsbOverCurrentPinSkip,                            // Port05: NC
+  UsbOverCurrentPinSkip,                            // Port06: NC
+  UsbOverCurrentPinSkip,                            // Port07: NC
+  UsbOverCurrentPinSkip,                            // Port08: NC
+  UsbOverCurrentPinSkip,                            // Port09: NC
+  UsbOverCurrentPinSkip                             // Port10: NC
+};
+
+USB2_PHY_PARAMETERS  TypeAowandaUsb20AfeParams[PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS] = {
+  { 3, 0, 3, 1 },                       // PP0
+  { 5, 0, 3, 1 },                       // PP1
+  { 3, 0, 3, 1 },                       // PP2
+  { 0, 5, 1, 1 },                       // PP3
+  { 3, 0, 3, 1 },                       // PP4
+  { 3, 0, 3, 1 },                       // PP5
+  { 3, 0, 3, 1 },                       // PP6
+  { 3, 0, 3, 1 },                       // PP7
+  { 2, 2, 1, 0 },                       // PP8
+  { 6, 0, 2, 1 },                       // PP9
+  { 2, 2, 1, 0 },                       // PP10
+  { 6, 0, 2, 1 },                       // PP11
+  { 0, 5, 1, 1 },                       // PP12
+  { 7, 0, 2, 1 },                       // PP13
+};
+
+EFI_STATUS
+TypeAowandaPlatformUsbOcUpdateCallback (
+  IN OUT   USB_OVERCURRENT_PIN  **Usb20OverCurrentMappings,
+  IN OUT   USB_OVERCURRENT_PIN  **Usb30OverCurrentMappings,
+  IN OUT   USB2_PHY_PARAMETERS  **Usb20AfeParams
+  )
+{
+  *Usb20OverCurrentMappings = &TypeAowandaUsb20OverCurrentMappings[0];
+  *Usb30OverCurrentMappings = &TypeAowandaUsb30OverCurrentMappings[0];
+
+  *Usb20AfeParams = TypeAowandaUsb20AfeParams;
+  return EFI_SUCCESS;
+}
+
+PLATFORM_USBOC_UPDATE_TABLE  TypeAowandaUsbOcUpdate =
+{
+  PLATFORM_USBOC_UPDATE_SIGNATURE,
+  PLATFORM_USBOC_UPDATE_VERSION,
+  TypeAowandaPlatformUsbOcUpdateCallback
+};
+
+EFI_STATUS
+TypeAowandaPlatformUpdateUsbOcMappings (
+  IN UBA_CONFIG_DATABASE_PPI  *UbaConfigPpi
+  )
+{
+  // #
+  // # USB, see PG 104 in GZP SCH
+  // #
+
+  //  USB2      USB3      Port                            OC
+  //
+  // Port00:     PORT5     Back Panel                      ,OC0#
+  // Port01:     PORT2     Back Panel                      ,OC0#
+  // Port02:     PORT3     Back Panel                      ,OC1#
+  // Port03:     PORT0     NOT USED                        ,NA
+  // Port04:               BMC1.0                          ,NA
+  // Port05:               INTERNAL_2X5_A                  ,OC2#
+  // Port06:               INTERNAL_2X5_A                  ,OC2#
+  // Port07:               NOT USED                        ,NA
+  // Port08:               EUSB (AKA SSD)                  ,NA
+  // Port09:               INTERNAL_TYPEA                  ,OC6#
+  // Port10:     PORT1     Front Panel                     ,OC5#
+  // Port11:               NOT USED                        ,NA
+  // Port12:               BMC2.0                          ,NA
+  // Port13:     PORT4     Front Panel                     ,OC5#
+
+  EFI_STATUS  Status;
+
+  Status = UbaConfigPpi->AddData (
+                                  UbaConfigPpi,
+                                  &gPeiPlatformUbaOcConfigDataGuid,
+                                  &TypeAowandaUsbOcUpdate,
+                                  sizeof (TypeAowandaUsbOcUpdate)
+                                  );
+
+  return Status;
+}

+ 195 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/build_board.py

@@ -0,0 +1,195 @@
+# @ build_board.py
+# Extensions for building Aowanda using build_bios.py
+#
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2022, American Megatrends International LLC. <BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+"""
+This module serves as a sample implementation of the build extension
+scripts
+"""
+
+import os
+import sys
+
+def pre_build_ex(config, functions):
+    """Additional Pre BIOS build function
+
+    :param config: The environment variables to be used in the build process
+    :type config: Dictionary
+    :param functions: A dictionary of function pointers
+    :type functions: Dictionary
+    :returns: nothing
+    """
+    print("pre_build_ex")
+
+    config["BUILD_DIR_PATH"] = os.path.join(config["WORKSPACE"],
+                                            'Build',
+                                            config["PLATFORM_BOARD_PACKAGE"],
+                                            "{}_{}".format(
+                                                config["TARGET"],
+                                                config["TOOL_CHAIN_TAG"]))
+    # set BUILD_DIR path
+    config["BUILD_DIR"] = os.path.join('Build',
+                                       config["PLATFORM_BOARD_PACKAGE"],
+                                       "{}_{}".format(
+                                           config["TARGET"],
+                                           config["TOOL_CHAIN_TAG"]))
+    config["BUILD_X64"] = os.path.join(config["BUILD_DIR_PATH"], 'X64')
+    config["BUILD_IA32"] = os.path.join(config["BUILD_DIR_PATH"], 'IA32')
+
+    if not os.path.isdir(config["BUILD_DIR_PATH"]):
+        try:
+            os.makedirs(config["BUILD_DIR_PATH"])
+        except OSError:
+            print("Error while creating Build folder")
+            sys.exit(1)
+
+    #@todo: Replace this with PcdFspModeSelection
+    if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE":
+        config["EXT_BUILD_FLAGS"] += " -D FSP_MODE=0"
+    else:
+        config["EXT_BUILD_FLAGS"] += " -D FSP_MODE=1"
+
+    if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE":
+        raise ValueError("FSP API Mode is currently unsupported on Ice Lake Xeon Scalable")
+
+    # Build the ACPI AML offset table *.offset.h
+    print("Info: re-generating PlatformOffset header files")
+
+    execute_script = functions.get("execute_script")
+
+    # AML offset arch is X64, not sure if it matters.
+    command = ["build", "-a", "X64", "-t", config["TOOL_CHAIN_TAG"], "-D", "MAX_SOCKET=" + config["MAX_SOCKET"]]
+
+    if config["EXT_BUILD_FLAGS"] and config["EXT_BUILD_FLAGS"] != "":
+        ext_build_flags = config["EXT_BUILD_FLAGS"].split(" ")
+        ext_build_flags = [x.strip() for x in ext_build_flags]
+        ext_build_flags = [x for x in ext_build_flags if x != ""]
+        command.extend(ext_build_flags)
+
+    aml_offsets_split = os.path.split(os.path.normpath(config["AML_OFFSETS_PATH"]))
+    command.append("-p")
+    command.append(os.path.normpath(config["AML_OFFSETS_PATH"]) + '.dsc')
+    command.append("-m")
+    command.append(os.path.join(aml_offsets_split[0], aml_offsets_split[1], aml_offsets_split[1] + '.inf'))
+    command.append("-y")
+    command.append(os.path.join(config["WORKSPACE"], "PreBuildReport.txt"))
+    command.append("--log=" + os.path.join(config["WORKSPACE"], "PreBuild.log"))
+
+    shell = True
+    if os.name == "posix":  # linux
+        shell = False
+
+    _, _, _, code = execute_script(command, config, shell=shell)
+    if code != 0:
+        print(" ".join(command))
+        print("Error re-generating PlatformOffset header files")
+        sys.exit(1)
+
+    # Build AmlGenOffset command to consume the *.offset.h and produce AmlOffsetTable.c for StaticSkuDataDxe use.
+
+    # Get destination path and filename from config
+    relative_file_path = os.path.normpath(config["STRIPPED_AML_OFFSETS_FILE_PATH"])     # get path relative to Platform/Intel
+    out_file_path = os.path.join(config["WORKSPACE_PLATFORM"], relative_file_path)      # full path to output file
+    out_file_dir = os.path.dirname(out_file_path)                                       # remove filename
+
+    out_file_root_ext = os.path.splitext(os.path.basename(out_file_path))               # root and extension of output file
+
+    # Get relative path for the generated offset.h file
+    relative_dsdt_file_path = os.path.normpath(config["DSDT_TABLE_FILE_PATH"])          # path relative to Platform/Intel
+    dsdt_file_root_ext = os.path.splitext(os.path.basename(relative_dsdt_file_path))    # root and extension of generated offset.h file
+
+    # Generate output directory if it doesn't exist
+    if not os.path.exists(out_file_dir):
+        os.mkdir(out_file_dir)
+
+    command = ["python",
+               os.path.join(config["MIN_PACKAGE_TOOLS"], "AmlGenOffset", "AmlGenOffset.py"),
+               "-d", "--aml_filter", config["AML_FILTER"],
+               "-o", out_file_path,
+               os.path.join(config["BUILD_X64"], aml_offsets_split[0], aml_offsets_split[1], aml_offsets_split[1], "OUTPUT", os.path.dirname(relative_dsdt_file_path), dsdt_file_root_ext[0] + ".offset.h")]
+
+    # execute the command
+    _, _, _, code = execute_script(command, config, shell=shell)
+    if code != 0:
+        print(" ".join(command))
+        print("Error re-generating PlatformOffset header files")
+        sys.exit(1)
+
+    print("GenOffset done")
+
+
+    return None
+
+def _merge_files(files, ofile):
+    with open(ofile, 'wb') as of:
+        for x in files:
+            if not os.path.exists(x):
+                return
+
+            with open(x, 'rb') as f:
+                of.write(f.read())
+
+def build_ex(config, functions):
+    """Additional BIOS build function
+
+    :param config: The environment variables to be used in the build process
+    :type config: Dictionary
+    :param functions: A dictionary of function pointers
+    :type functions: Dictionary
+    :returns: config dictionary
+    :rtype: Dictionary
+    """
+    print("build_ex")
+    fv_path = os.path.join(config["BUILD_DIR_PATH"], "FV")
+    binary_fd = os.path.join(fv_path, "BINARY.fd")
+    main_fd = os.path.join(fv_path, "MAIN.fd")
+    secpei_fd = os.path.join(fv_path, "SECPEI.fd")
+    board_fd = config["BOARD"].upper()
+    final_fd = os.path.join(fv_path, "{}.fd".format(board_fd))
+    _merge_files((binary_fd, main_fd, secpei_fd), final_fd)
+    return None
+
+
+def post_build_ex(config, functions):
+    """Additional Post BIOS build function
+
+    :param config: The environment variables to be used in the post
+        build process
+    :type config: Dictionary
+    :param functions: A dictionary of function pointers
+    :type functions: Dictionary
+    :returns: config dictionary
+    :rtype: Dictionary
+    """
+    print("post_build_ex")
+    fv_path = os.path.join(config["BUILD_DIR_PATH"], "FV")
+    board_fd = config["BOARD"].upper()
+    final_fd = os.path.join(fv_path, "{}.fd".format(board_fd))
+    final_ifwi = os.path.join(fv_path, "{}.bin".format(board_fd))
+
+    ifwi_ingredients_path = os.path.join(config["WORKSPACE_PLATFORM_BIN"], "Ifwi", config["BOARD"])
+    flash_descriptor = os.path.join(ifwi_ingredients_path, "FlashDescriptor.bin")
+    intel_me = os.path.join(ifwi_ingredients_path, "Me.bin")
+    _merge_files((flash_descriptor, intel_me, final_fd), final_ifwi)
+    if os.path.isfile(final_fd):
+        print("IFWI image can be found at {}".format(final_ifwi))
+    return None
+
+
+def clean_ex(config, functions):
+    """Additional clean function
+
+    :param config: The environment variables to be used in the build process
+    :type config: Dictionary
+    :param functions: A dictionary of function pointers
+    :type functions: Dictionary
+    :returns: config dictionary
+    :rtype: Dictionary
+    """
+    print("clean_ex")
+    return None

+ 52 - 0
Platform/Intel/WhitleyOpenBoardPkg/Aowanda/build_config.cfg

@@ -0,0 +1,52 @@
+# @ build_config.cfg
+# This is the Aowanda board specific build settings
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2022, American Megatrends International LLC. <BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+[CONFIG]
+WORKSPACE_PLATFORM_BIN = edk2-non-osi/Platform/Intel/WhitleyOpenBoardBinPkg
+EDK_SETUP_OPTION =
+openssl_path =
+PLATFORM_BOARD_PACKAGE = WhitleyOpenBoardPkg
+PROJECT = WhitleyOpenBoardPkg/Aowanda
+BOARD = Aowanda
+FLASH_MAP_FDF = WhitleyOpenBoardPkg/FspFlashOffsets.fdf
+PROJECT_DSC = WhitleyOpenBoardPkg/Aowanda/PlatformPkg.dsc
+BOARD_PKG_PCD_DSC = WhitleyOpenBoardPkg/PlatformPkgConfig.dsc
+ADDITIONAL_SCRIPTS = WhitleyOpenBoardPkg/Aowanda/build_board.py
+PrepRELEASE = DEBUG
+SILENT_MODE = FALSE
+EXT_CONFIG_CLEAR =
+CapsuleBuild = FALSE
+EXT_BUILD_FLAGS = -D CPUTARGET=ICX -D RP_PKG=WhitleyOpenBoardPkg -D SILICON_PKG=WhitleySiliconPkg -D PCD_DYNAMIC_AS_DYNAMICEX -D MAX_CORE=64 -D MAX_THREAD=2 -D PLATFORM_PKG=MinPlatformPkg
+MAX_SOCKET = 4
+CAPSULE_BUILD = 0
+TARGET = DEBUG
+TARGET_SHORT = D
+PERFORMANCE_BUILD = FALSE
+FSP_WRAPPER_BUILD = TRUE
+FSP_BIN_PKG = WhitleyFspBinPkg
+FSP_PKG_NAME = WhitleyFspPkg
+FSP_BINARY_BUILD = FALSE
+FSP_TEST_RELEASE = FALSE
+SECURE_BOOT_ENABLE = FALSE
+BIOS_INFO_GUID = 4A4CA1C6-871C-45BB-8801-6910A7AA5807
+
+#
+# AML offset table generation configuration options
+# All paths should use / and be relative to edk2-platforms/Platform/Intel
+#
+# AML_FILTER                      - AML filter is used to strip out unused AML offset data
+# AML_OFFSETS_PATH                - Path to INF file that builds AML offsets C source file
+#   The directory name, DSC file name, INF file name, and BASE_NAME must match identically
+# DSDT_TABLE_FILE_PATH            - Path to DSDT ASL file for the board
+# STRIPPED_AML_OFFSETS_FILE_PATH  - Target AML offset data file consumed by UBA driver
+#
+AML_FILTER = \"PSYS\" .\.DRVT\" .\.FIX[0-9,A-Z] BBI[0] BBU[0] CRCM BAR0 .\.CCT[0-9A-Z]\" .\.CFH[0-9A-Z]\" .\.FXCD\" .\.FXST\" .\.FXIN\" .\.FXOU\" .\.FXBS\" .\.FXFH\" .\.CENA\" .\.DRVT\" .\.CFIS\" {NULL };
+AML_OFFSETS_PATH = WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets
+DSDT_TABLE_FILE_PATH = WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm.asl
+STRIPPED_AML_OFFSETS_FILE_PATH = WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AmlOffsetTable.c

+ 2 - 1
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec

@@ -4,7 +4,7 @@
 #
 # @copyright
 # Copyright 2008 - 2021 Intel Corporation. <BR>
-# Copyright (c) 2021, American Megatrends International LLC. <BR>
+# Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
@@ -139,6 +139,7 @@
   gEfiPlatformTypeWilsonCitySMTProtocolGuid           = { 0xEE55562D, 0x4001, 0xFC27, { 0xDF, 0x16, 0x7B, 0x90, 0xEB, 0xE1, 0xAB, 0x04 } }
   gEfiPlatformTypeCooperCityRPProtocolGuid            = { 0x45c302e1, 0x4b86, 0x89be, { 0xab, 0x0f, 0x5e, 0xb5, 0x57, 0xdf, 0xe8, 0xd8 } }
   gEfiPlatformTypeJunctionCityProtocolGuid            = { 0xB1C2B1C9, 0xB606, 0x4B62, { 0x9D, 0x78, 0xCB, 0xD6, 0x0F, 0xF9, 0x0D, 0x0C } }
+  gEfiPlatformTypeAowandaProtocolGuid                 = { 0x65231A3C, 0xC343, 0x4C7E, { 0xA4, 0x5E, 0x0F, 0x99, 0x74, 0xA6, 0x90, 0x83 } }
 
 #
 # UBA_END

+ 11 - 1
Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c

@@ -3,7 +3,7 @@
 
   @copyright
   Copyright 2014 - 2021 Intel Corporation.
-  Copyright (c) 2021, American Megatrends International LLC. <BR>
+  Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -99,6 +99,16 @@ BoardInitDxeDriverEntry (
       ASSERT_EFI_ERROR (Status);
       break;
 
+   case TypeAowanda:
+        Status = gBS->InstallProtocolInterface (
+          &Handle,
+          &gEfiPlatformTypeAowandaProtocolGuid,
+          EFI_NATIVE_INTERFACE,
+          NULL
+          );
+        ASSERT_EFI_ERROR (Status);
+        break;
+
     default:
       // CAN'T GO TO HERE.
       ASSERT (FALSE);

+ 2 - 1
Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf

@@ -3,7 +3,7 @@
 #
 # @copyright
 # Copyright 2014 - 2021 Intel Corporation.
-# Copyright (c) 2021, American Megatrends International LLC. <BR>
+# Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
@@ -64,6 +64,7 @@
   gEfiPlatformTypeWilsonCitySMTProtocolGuid              #PRODUCER
   gEfiPlatformTypeCooperCityRPProtocolGuid               #PRODUCER
   gEfiPlatformTypeJunctionCityProtocolGuid               #PRODUCER
+  gEfiPlatformTypeAowandaProtocolGuid                    #PRODUCER
 
 [FixedPcd]
   gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount

+ 3 - 1
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf

@@ -3,6 +3,7 @@
 #
 # @copyright
 # Copyright 2018 - 2022 Intel Corporation. <BR>
+# Copyright (c) 2022, American Megatrends International LLC. <BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
@@ -56,4 +57,5 @@
 [Depex]
   gEfiPlatformTypeWilsonCitySMTProtocolGuid OR
   gEfiPlatformTypeWilsonCityRPProtocolGuid  OR
-  gEfiPlatformTypeJunctionCityProtocolGuid
+  gEfiPlatformTypeJunctionCityProtocolGuid  OR
+  gEfiPlatformTypeAowandaProtocolGuid

+ 2 - 1
Platform/Intel/build.cfg

@@ -2,7 +2,7 @@
 # This is the main/default build configuration file
 #
 # Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>
-# Copyright (c) 2021, American Megatrends International LLC.<BR>
+# Copyright (c) 2021 - 2022, American Megatrends International LLC.<BR>
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 
@@ -68,3 +68,4 @@ CooperCityRvp = WhitleyOpenBoardPkg/CooperCityRvp/build_config.cfg
 WilsonCityRvp = WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg
 BoardTiogaPass = PurleyOpenBoardPkg/BoardTiogaPass/build_config.cfg
 JunctionCity = WhitleyOpenBoardPkg/JunctionCity/build_config.cfg
+Aowanda = WhitleyOpenBoardPkg/Aowanda/build_config.cfg

+ 2 - 1
Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h

@@ -2,7 +2,7 @@
 
   @copyright
   Copyright 2020 - 2021 Intel Corporation. <BR>
-  Copyright (c) 2021, American Megatrends International LLC. <BR>
+  Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -65,6 +65,7 @@ typedef enum {
   TypeBigPineKey,
   TypeExperWorkStationRP,
   TypeJunctionCity,
+  TypeAowanda,
   EndOfEfiPlatformTypeEnum,
   //
   // Vendor board range currently starts at 0x80