IioCfgUpdateDxe.h 3.8 KB

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  1. /** @file
  2. @copyright
  3. Copyright 2016 - 2021 Intel Corporation. <BR>
  4. Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #ifndef _IIOCFG_UPDATE_DXE_H_
  8. #define _IIOCFG_UPDATE_DXE_H_
  9. #include <Base.h>
  10. #include <Uefi.h>
  11. #include <Protocol/UbaCfgDb.h>
  12. #include <Library/UefiDriverEntryPoint.h>
  13. #include <Library/UefiBootServicesTableLib.h>
  14. #include <Library/DebugLib.h>
  15. #include <Library/BaseLib.h>
  16. #include <Library/BaseMemoryLib.h>
  17. #include <Library/MemoryAllocationLib.h>
  18. #include <Library/PciLib.h>
  19. #include <Library/UbaIioConfigLib.h>
  20. #include <IioPlatformData.h>
  21. typedef enum {
  22. Iio_Socket0 = 0,
  23. Iio_Socket1,
  24. Iio_Socket2,
  25. Iio_Socket3,
  26. Iio_Socket4,
  27. Iio_Socket5,
  28. Iio_Socket6,
  29. Iio_Socket7
  30. } IIO_SOCKETS;
  31. typedef enum {
  32. Iio_Iou0 = 0,
  33. Iio_Iou1,
  34. Iio_Iou2,
  35. Iio_Mcp0,
  36. Iio_Mcp1,
  37. Iio_IouMax
  38. } IIO_IOUS;
  39. typedef enum {
  40. VPP_PORT_0 = 0,
  41. VPP_PORT_1,
  42. VPP_PORT_2,
  43. VPP_PORT_3
  44. } VPP_PORT;
  45. #define ENABLE 1
  46. #define DISABLE 0
  47. #define NO_SLT_IMP 0xFF
  48. #define SLT_IMP 1
  49. #define HIDE 1
  50. #define NOT_HIDE 0
  51. #define VPP_PORT_0 0
  52. #define VPP_PORT_1 1
  53. #define VPP_PORT_MAX 0xFF
  54. #define VPP_ADDR_MAX 0xFF
  55. #define PWR_VAL_MAX 0xFF
  56. #define PWR_SCL_MAX 0xFF
  57. static IIO_BIFURCATION_DATA_ENTRY IioBifurcationTable[] =
  58. {
  59. { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 },
  60. { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 },
  61. { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 },
  62. { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 },
  63. { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 },
  64. { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxx8xxx8 },
  65. { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 },
  66. { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 },
  67. { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 },
  68. { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 },
  69. };
  70. static IIO_SLOT_CONFIG_DATA_ENTRY IioSlotTable[] = {
  71. // Port | Slot | Inter | Power Limit | Power Limit | Hot | Vpp | Vpp | PcieSSD | PcieSSD | PcieSSD | Hidden
  72. // Index | | lock | Scale | Value | Plug | Port | Addr | Cap | VppPort | VppAddr |
  73. { PORT_1A_INDEX, 1 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x4C , NOT_HIDE},
  74. { PORT_2A_INDEX, 7 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX, VPP_ADDR_MAX , NOT_HIDE},
  75. { PORT_3A_INDEX, 2 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 , NOT_HIDE},
  76. { SOCKET_1_INDEX +
  77. PORT_0_INDEX , NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX, VPP_ADDR_MAX , HIDE },
  78. // Slot 4 supports HP: PCA9554 (CPU1) Address 0x40, SCH (Rev 0.604) P 121 (MRL in J287)
  79. { SOCKET_1_INDEX +
  80. PORT_1A_INDEX, 4 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 , NOT_HIDE},
  81. { SOCKET_1_INDEX +
  82. PORT_1C_INDEX, 3 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 , NOT_HIDE},
  83. { SOCKET_1_INDEX +
  84. PORT_2A_INDEX, 6 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_1 , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x44 , NOT_HIDE},
  85. { SOCKET_1_INDEX +
  86. PORT_3A_INDEX, 5 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX, VPP_ADDR_MAX , NOT_HIDE},
  87. };
  88. #endif //_IIOCFG_UPDATE_DXE_H_