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Silicon/NXP/LS1043A: Fix the RCW bits' parsing

For LS1043A SOC the DCFG registers are read in big endian format.
After Reading the registers in code we have the registers in Little
Endian Bit format i.e. LSBit 0.

However, the RCW bits in RCWSR registers in LS1043A SOC are in MSBit 0
format.

Currently, we are parsing the RCW bits in LE bit format i.e. LSBit 0.
Therefore, Fix the RCW bits' parsing as per MSBit 0.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Pankaj Bansal 3 éve
szülő
commit
bd4308bf9c
1 módosított fájl, 1 hozzáadás és 1 törlés
  1. 1 1
      Silicon/NXP/LS1043A/Include/Soc.h

+ 1 - 1
Silicon/NXP/LS1043A/Include/Soc.h

@@ -78,7 +78,7 @@ Bit(s) | Field Name  | Description                  | Notes/comments
 
   which is why the RCW bits in RCWSR registers are parsed this way
 **/
-#define SYS_PLL_RAT(x)  (((x) & 0x7c) >> 2) // Bits 2-6
+#define SYS_PLL_RAT(x)  (((x) >> 25) & 0x1f) // Bits 2-6
 
 typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG;