Soc.h 3.0 KB

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  1. /** @file
  2. Copyright 2020 NXP
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #ifndef SOC_H__
  6. #define SOC_H__
  7. #include <Chassis.h>
  8. /**
  9. Soc Memory Map
  10. **/
  11. #define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000
  12. #define LS1043A_DRAM0_SIZE SIZE_2GB
  13. #define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000
  14. #define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB
  15. #define LS1043A_CCSR_PHYS_ADDRESS 0x1000000
  16. #define LS1043A_CCSR_SIZE 0xF000000
  17. #define LS1043A_IFC0_PHYS_ADDRESS 0x60000000
  18. #define LS1043A_IFC0_SIZE SIZE_512MB
  19. #define LS1043A_IFC1_PHYS_ADDRESS 0x620000000
  20. #define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB
  21. #define LS1043A_QSPI_PHYS_ADDRESS 0x40000000
  22. #define LS1043A_QSPI_SIZE SIZE_512MB
  23. #define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000
  24. #define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB
  25. #define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000
  26. #define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB
  27. #define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000
  28. #define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000
  29. #define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000
  30. #define LS1043A_PCI_SIZE SIZE_32GB
  31. #define LS1043A_I2C0_PHYS_ADDRESS 0x2180000
  32. #define LS1043A_I2C_SIZE 0x10000
  33. #define LS1043A_I2C_NUM_CONTROLLERS 4
  34. #define LS1043A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
  35. //SVR
  36. #define SVR_LS1043A 0x879200
  37. /**
  38. Reset Control Word (RCW) Bits
  39. RCWSR contains the Reset Configuration Word (RCW) information written with
  40. values read from flash memory by the device at power-on reset and read-only
  41. upon exiting reset.
  42. RCW bits in RCWSR registers are mirror of bit position in Little Endian (LE)
  43. RCW Bits |
  44. in RCWSR |
  45. (MSBit 0)| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
  46. ------------------------------------------------------------------------------------------------
  47. LE | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  48. (LSBit 0)|
  49. Moreover the RCW bits are to be interpreted in below fasion
  50. Bit(s) | Field Name | Description | Notes/comments
  51. ----------------------------------------------------------------------
  52. 2-6 | SYS_PLL_RAT | System PLL Multiplier/Ratio | This field selects the platform
  53. | | | clock:SYSCLK ratio.
  54. | | | 0_0011 3:1
  55. | | | 0_0100 4:1
  56. | | | 0_1101 13:1
  57. | | | 0_1111 15:1
  58. | | | 1_0000 16:1
  59. which is why the RCW bits in RCWSR registers are parsed this way
  60. **/
  61. #define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6
  62. typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG;
  63. #endif // SOC_H__