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ProcessorPkg/Library: Add RISC-V exception library

Initial RISC-V Supervisor Mode trap handler.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Abner Chang 4 年之前
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+ 43 - 0
Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf

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+## @file
+#  RISC-V CPU Exception Handler Library
+#
+#  Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+  INF_VERSION                    = 0x0001001b
+  BASE_NAME                      = CpuExceptionHandlerLib
+  MODULE_UNI_FILE                = CpuExceptionHandlerLib.uni
+  FILE_GUID                      = 16309FCF-E900-459C-B071-052118394D11
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = CpuExceptionHandlerLib
+  CONSTRUCTOR                    = CpuExceptionHandlerLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = RISCV64
+#
+
+[Sources.RISCV64]
+  SupervisorTrapHandler.S
+
+[Sources.common]
+  CpuExceptionHandlerLib.c
+  CpuExceptionHandlerLib.h
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  RiscVCpuLib
+  UefiBootServicesTableLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+

+ 194 - 0
Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c

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+/** @file
+  RISC-V Exception Handler library implementition.
+
+  Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/CpuExceptionHandlerLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_types.h>
+
+#include "CpuExceptionHandlerLib.h"
+
+STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2];
+
+/**
+  Initializes all CPU exceptions entries and provides the default exception handlers.
+
+  Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
+  persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
+  If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
+  If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
+
+  @param[in]  VectorInfo    Pointer to reserved vector list.
+
+  @retval EFI_SUCCESS           CPU Exception Entries have been successfully initialized
+                                with default exception handlers.
+  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
+  @retval EFI_UNSUPPORTED       This function is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuExceptionHandlers (
+  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL
+  )
+{
+  return EFI_SUCCESS;
+}
+
+/**
+  Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.
+
+  Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
+  persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
+  If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
+  If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
+
+  @param[in]  VectorInfo    Pointer to reserved vector list.
+
+  @retval EFI_SUCCESS           All CPU interrupt/exception entries have been successfully initialized
+                                with default interrupt/exception handlers.
+  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
+  @retval EFI_UNSUPPORTED       This function is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuInterruptHandlers (
+  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL
+  )
+{
+  return EFI_SUCCESS;
+}
+
+/**
+  Registers a function to be called from the processor interrupt handler.
+
+  This function registers and enables the handler specified by InterruptHandler for a processor
+  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
+  handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
+  The installed handler is called once for each processor interrupt or exception.
+  NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or
+  InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED returned.
+
+  @param[in]  InterruptType     Defines which interrupt or exception to hook.
+  @param[in]  InterruptHandler  A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
+                                when a processor interrupt occurs. If this parameter is NULL, then the handler
+                                will be uninstalled.
+
+  @retval EFI_SUCCESS           The handler for the processor interrupt was successfully installed or uninstalled.
+  @retval EFI_ALREADY_STARTED   InterruptHandler is not NULL, and a handler for InterruptType was
+                                previously installed.
+  @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
+                                previously installed.
+  @retval EFI_UNSUPPORTED       The interrupt specified by InterruptType is not supported,
+                                or this function is not supported.
+**/
+EFI_STATUS
+EFIAPI
+RegisterCpuInterruptHandler (
+  IN EFI_EXCEPTION_TYPE            InterruptType,
+  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler
+  )
+{
+
+  DEBUG ((DEBUG_INFO, "%a: Type:%x Handler: %x\n", __FUNCTION__, InterruptType, InterruptHandler));
+  mInterruptHandlers[InterruptType] = InterruptHandler;
+  return EFI_SUCCESS;
+}
+/**
+  Machine mode trap handler.
+
+  @param[in]  SmodeTrapReg     Registers before trap occurred.
+
+**/
+VOID
+RiscVSupervisorModeTrapHandler (
+  SMODE_TRAP_REGISTERS *SmodeTrapReg
+  )
+{
+  UINTN SCause;
+  EFI_SYSTEM_CONTEXT RiscVSystemContext;
+
+  RiscVSystemContext.SystemContextRiscV64 = (EFI_SYSTEM_CONTEXT_RISCV64 *)SmodeTrapReg;
+  //
+  // Check scasue register.
+  //
+  SCause = (UINTN)csr_read(RISCV_CSR_SUPERVISOR_SCAUSE);
+  if ((SCause & (1UL << (sizeof (UINTN) * 8- 1))) != 0) {
+    //
+    // This is interrupt event.
+    //
+    SCause &= ~(1UL << (sizeof (UINTN) * 8- 1));
+    if((SCause == SCAUSE_SUPERVISOR_TIMER_INT) && (mInterruptHandlers[EXCEPT_RISCV_TIMER_INT] != NULL)) {
+      mInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, RiscVSystemContext);
+    }
+  }
+}
+
+/**
+  Initializes all CPU exceptions entries with optional extra initializations.
+
+  By default, this method should include all functionalities implemented by
+  InitializeCpuExceptionHandlers(), plus extra initialization works, if any.
+  This could be done by calling InitializeCpuExceptionHandlers() directly
+  in this method besides the extra works.
+
+  InitData is optional and its use and content are processor arch dependent.
+  The typical usage of it is to convey resources which have to be reserved
+  elsewhere and are necessary for the extra initializations of exception.
+
+  @param[in]  VectorInfo    Pointer to reserved vector list.
+  @param[in]  InitData      Pointer to data optional for extra initializations
+                            of exception.
+
+  @retval EFI_SUCCESS             The exceptions have been successfully
+                                  initialized.
+  @retval EFI_INVALID_PARAMETER   VectorInfo or InitData contains invalid
+                                  content.
+  @retval EFI_UNSUPPORTED         This function is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuExceptionHandlersEx (
+  IN EFI_VECTOR_HANDOFF_INFO            *VectorInfo OPTIONAL,
+  IN CPU_EXCEPTION_INIT_DATA            *InitData OPTIONAL
+  )
+{
+  return InitializeCpuExceptionHandlers (VectorInfo);
+}
+
+/**
+  The constructor function to initial interrupt handlers in
+  RISCV_MACHINE_MODE_CONTEXT.
+
+  @param  ImageHandle   The firmware allocated handle for the EFI image.
+  @param  SystemTable   A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS   The destructor completed successfully.
+  @retval Other value   The destructor did not complete successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuExceptionHandlerLibConstructor (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  //
+  // Set Superviosr mode trap handler.
+  //
+  csr_write(CSR_STVEC, SupervisorModeTrap);
+
+  return EFI_SUCCESS;
+}

+ 107 - 0
Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h

@@ -0,0 +1,107 @@
+/**@file
+
+  RISC-V Exception Handler library definition file.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_CPU_EXECPTION_HANDLER_LIB_H_
+#define RISCV_CPU_EXECPTION_HANDLER_LIB_H_
+
+extern void SupervisorModeTrap(void);
+
+//
+// Index of SMode trap register
+//
+#define SMODE_TRAP_REGS_zero          0
+#define SMODE_TRAP_REGS_ra            1
+#define SMODE_TRAP_REGS_sp            2
+#define SMODE_TRAP_REGS_gp            3
+#define SMODE_TRAP_REGS_tp            4
+#define SMODE_TRAP_REGS_t0            5
+#define SMODE_TRAP_REGS_t1            6
+#define SMODE_TRAP_REGS_t2            7
+#define SMODE_TRAP_REGS_s0            8
+#define SMODE_TRAP_REGS_s1            9
+#define SMODE_TRAP_REGS_a0            10
+#define SMODE_TRAP_REGS_a1            11
+#define SMODE_TRAP_REGS_a2            12
+#define SMODE_TRAP_REGS_a3            13
+#define SMODE_TRAP_REGS_a4            14
+#define SMODE_TRAP_REGS_a5            15
+#define SMODE_TRAP_REGS_a6            16
+#define SMODE_TRAP_REGS_a7            17
+#define SMODE_TRAP_REGS_s2            18
+#define SMODE_TRAP_REGS_s3            19
+#define SMODE_TRAP_REGS_s4            20
+#define SMODE_TRAP_REGS_s5            21
+#define SMODE_TRAP_REGS_s6            22
+#define SMODE_TRAP_REGS_s7            23
+#define SMODE_TRAP_REGS_s8            24
+#define SMODE_TRAP_REGS_s9            25
+#define SMODE_TRAP_REGS_s10           26
+#define SMODE_TRAP_REGS_s11           27
+#define SMODE_TRAP_REGS_t3            28
+#define SMODE_TRAP_REGS_t4            29
+#define SMODE_TRAP_REGS_t5            30
+#define SMODE_TRAP_REGS_t6            31
+#define SMODE_TRAP_REGS_sepc          32
+#define SMODE_TRAP_REGS_sstatus       33
+#define SMODE_TRAP_REGS_sie           34
+#define SMODE_TRAP_REGS_last          35
+
+#define SMODE_TRAP_REGS_OFFSET(x) ((SMODE_TRAP_REGS_##x) * __SIZEOF_POINTER__)
+#define SMODE_TRAP_REGS_SIZE SMODE_TRAP_REGS_OFFSET(last)
+
+#pragma pack(1)
+typedef struct {
+//
+// Below are follow the format of EFI_SYSTEM_CONTEXT
+//
+    RISC_V_REGS_PROTOTYPE zero;
+    RISC_V_REGS_PROTOTYPE ra;
+    RISC_V_REGS_PROTOTYPE sp;
+    RISC_V_REGS_PROTOTYPE gp;
+    RISC_V_REGS_PROTOTYPE tp;
+    RISC_V_REGS_PROTOTYPE t0;
+    RISC_V_REGS_PROTOTYPE t1;
+    RISC_V_REGS_PROTOTYPE t2;
+    RISC_V_REGS_PROTOTYPE s0;
+    RISC_V_REGS_PROTOTYPE s1;
+    RISC_V_REGS_PROTOTYPE a0;
+    RISC_V_REGS_PROTOTYPE a1;
+    RISC_V_REGS_PROTOTYPE a2;
+    RISC_V_REGS_PROTOTYPE a3;
+    RISC_V_REGS_PROTOTYPE a4;
+    RISC_V_REGS_PROTOTYPE a5;
+    RISC_V_REGS_PROTOTYPE a6;
+    RISC_V_REGS_PROTOTYPE a7;
+    RISC_V_REGS_PROTOTYPE s2;
+    RISC_V_REGS_PROTOTYPE s3;
+    RISC_V_REGS_PROTOTYPE s4;
+    RISC_V_REGS_PROTOTYPE s5;
+    RISC_V_REGS_PROTOTYPE s6;
+    RISC_V_REGS_PROTOTYPE s7;
+    RISC_V_REGS_PROTOTYPE s8;
+    RISC_V_REGS_PROTOTYPE s9;
+    RISC_V_REGS_PROTOTYPE s10;
+    RISC_V_REGS_PROTOTYPE s11;
+    RISC_V_REGS_PROTOTYPE t3;
+    RISC_V_REGS_PROTOTYPE t4;
+    RISC_V_REGS_PROTOTYPE t5;
+    RISC_V_REGS_PROTOTYPE t6;
+//
+// Below are the additional information to
+// EFI_SYSTEM_CONTEXT, private to supervisor mode trap
+// and not public to EFI environment.
+//
+    RISC_V_REGS_PROTOTYPE sepc;
+    RISC_V_REGS_PROTOTYPE sstatus;
+    RISC_V_REGS_PROTOTYPE sie;
+} SMODE_TRAP_REGISTERS;
+#pragma pack()
+
+#endif

+ 13 - 0
Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni

@@ -0,0 +1,13 @@
+// /** @file
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "RISC-V CPU Exception Handler Librarys."
+
+#string STR_MODULE_DESCRIPTION          #language en-US "RISC-V CPU Exception Handler Librarys."
+

+ 112 - 0
Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S

@@ -0,0 +1,112 @@
+/** @file
+  RISC-V Processor supervisor mode trap handler
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <RiscVImpl.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_trap.h>
+
+#include "CpuExceptionHandlerLib.h"
+
+  .align 3
+  .section .entry, "ax", %progbits
+  .globl SupervisorModeTrap
+SupervisorModeTrap:
+  addi sp, sp, -SMODE_TRAP_REGS_SIZE
+
+  /* Save all general regisers except SP */
+  sd    t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
+
+  csrr  t0, RISCV_CSR_SUPERVISOR_SSTATUS
+  and   t0, t0, (1 << SSTATUS_SIE_BIT_POSITION) | (1 << SSTATUS_SPP_BIT_POSITION)
+  sd    t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)
+  csrr  t0, RISCV_CSR_SUPERVISOR_SEPC
+  sd    t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)
+  csrr  t0, RISCV_CSR_SUPERVISOR_SIE
+  sd    t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)
+  ld    t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
+
+  sd    ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)
+  sd    gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)
+  sd    tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)
+  sd    t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)
+  sd    t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)
+  sd    s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)
+  sd    s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)
+  sd    a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)
+  sd    a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)
+  sd    a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)
+  sd    a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)
+  sd    a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)
+  sd    a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)
+  sd    a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)
+  sd    a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)
+  sd    s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)
+  sd    s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)
+  sd    s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)
+  sd    s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)
+  sd    s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)
+  sd    s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)
+  sd    s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)
+  sd    s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)
+  sd    s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)
+  sd    s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)
+  sd    t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)
+  sd    t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)
+  sd    t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)
+  sd    t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)
+
+  /* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */
+  call  RiscVSupervisorModeTrapHandler
+
+  /* Restore all general regisers except SP */
+  ld    ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)
+  ld    gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)
+  ld    tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)
+  ld    t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)
+  ld    s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)
+  ld    s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)
+  ld    a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)
+  ld    a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)
+  ld    a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)
+  ld    a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)
+  ld    a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)
+  ld    a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)
+  ld    a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)
+  ld    a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)
+  ld    s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)
+  ld    s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)
+  ld    s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)
+  ld    s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)
+  ld    s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)
+  ld    s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)
+  ld    s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)
+  ld    s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)
+  ld    s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)
+  ld    s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)
+  ld    t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)
+  ld    t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)
+  ld    t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)
+  ld    t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)
+
+  ld    t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)
+  csrw  RISCV_CSR_SUPERVISOR_SEPC, t0
+  ld    t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)
+  csrw  RISCV_CSR_SUPERVISOR_SIE, t0
+  csrr  t0, RISCV_CSR_SUPERVISOR_SSTATUS
+  ld    t1, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)
+  or    t0, t0, t1
+  csrw  RISCV_CSR_SUPERVISOR_SSTATUS, t0
+  ld    t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)
+  ld    t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
+  addi  sp, sp, SMODE_TRAP_REGS_SIZE
+  sret