SupervisorTrapHandler.S 4.1 KB

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  1. /** @file
  2. RISC-V Processor supervisor mode trap handler
  3. Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <Base.h>
  7. #include <RiscVImpl.h>
  8. #include <sbi/riscv_asm.h>
  9. #include <sbi/riscv_encoding.h>
  10. #include <sbi/sbi_platform.h>
  11. #include <sbi/sbi_scratch.h>
  12. #include <sbi/sbi_trap.h>
  13. #include "CpuExceptionHandlerLib.h"
  14. .align 3
  15. .section .entry, "ax", %progbits
  16. .globl SupervisorModeTrap
  17. SupervisorModeTrap:
  18. addi sp, sp, -SMODE_TRAP_REGS_SIZE
  19. /* Save all general regisers except SP */
  20. sd t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
  21. csrr t0, RISCV_CSR_SUPERVISOR_SSTATUS
  22. and t0, t0, (1 << SSTATUS_SIE_BIT_POSITION) | (1 << SSTATUS_SPP_BIT_POSITION)
  23. sd t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)
  24. csrr t0, RISCV_CSR_SUPERVISOR_SEPC
  25. sd t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)
  26. csrr t0, RISCV_CSR_SUPERVISOR_SIE
  27. sd t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)
  28. ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
  29. sd ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)
  30. sd gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)
  31. sd tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)
  32. sd t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)
  33. sd t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)
  34. sd s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)
  35. sd s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)
  36. sd a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)
  37. sd a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)
  38. sd a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)
  39. sd a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)
  40. sd a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)
  41. sd a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)
  42. sd a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)
  43. sd a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)
  44. sd s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)
  45. sd s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)
  46. sd s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)
  47. sd s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)
  48. sd s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)
  49. sd s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)
  50. sd s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)
  51. sd s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)
  52. sd s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)
  53. sd s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)
  54. sd t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)
  55. sd t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)
  56. sd t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)
  57. sd t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)
  58. /* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */
  59. call RiscVSupervisorModeTrapHandler
  60. /* Restore all general regisers except SP */
  61. ld ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)
  62. ld gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)
  63. ld tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)
  64. ld t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)
  65. ld s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)
  66. ld s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)
  67. ld a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)
  68. ld a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)
  69. ld a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)
  70. ld a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)
  71. ld a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)
  72. ld a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)
  73. ld a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)
  74. ld a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)
  75. ld s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)
  76. ld s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)
  77. ld s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)
  78. ld s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)
  79. ld s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)
  80. ld s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)
  81. ld s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)
  82. ld s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)
  83. ld s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)
  84. ld s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)
  85. ld t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)
  86. ld t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)
  87. ld t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)
  88. ld t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)
  89. ld t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)
  90. csrw RISCV_CSR_SUPERVISOR_SEPC, t0
  91. ld t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)
  92. csrw RISCV_CSR_SUPERVISOR_SIE, t0
  93. csrr t0, RISCV_CSR_SUPERVISOR_SSTATUS
  94. ld t1, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)
  95. or t0, t0, t1
  96. csrw RISCV_CSR_SUPERVISOR_SSTATUS, t0
  97. ld t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)
  98. ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
  99. addi sp, sp, SMODE_TRAP_REGS_SIZE
  100. sret