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RISC-V: Create opensbi firmware domains

Incorporate with opensbi to create three firmware domains,
- Boot firmware domain, which built with opensbi library as
  M-mode access only region.
- Firmware domain which includes PEI and DXE regions, the
  PMP attribute is readable, wriable and executable.
- EFI Variable region which is readable and writable.

Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Abner Chang 2 years ago
parent
commit
1ca07dd2fa

+ 8 - 1
Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf

@@ -3,7 +3,7 @@
 #  This is the the library which provides platform
 #  level opensbi functions follow RISC-V OpenSBI implementation.
 #
-#  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#  Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -54,3 +54,10 @@
 
   gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase
   gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock
+
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize

+ 71 - 13
Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c

@@ -1,7 +1,7 @@
 /*
  * SPDX-License-Identifier: BSD-2-Clause
  *
- * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
  *
  * Authors:
  *   Anup Patel <anup.patel@wdc.com>
@@ -10,6 +10,7 @@
 #include <libfdt.h>
 #include <PlatformOverride.h>
 #include <sbi/riscv_asm.h>
+#include <sbi/sbi_domain.h>
 #include <sbi/sbi_hartmask.h>
 #include <sbi/sbi_platform.h>
 #include <sbi/sbi_string.h>
@@ -185,20 +186,77 @@ static u64 generic_tlbr_flush_limit(void)
   return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT;
 }
 
+static int generic_system_reset_check(u32 reset_type, u32 reset_reason)
+{
+  if (generic_plat && generic_plat->system_reset_check)
+    return generic_plat->system_reset_check(reset_type,
+              reset_reason,
+              generic_plat_match);
+  return fdt_system_reset_check(reset_type, reset_reason);
+}
+
+static void generic_system_reset(u32 reset_type, u32 reset_reason)
+{
+  if (generic_plat && generic_plat->system_reset) {
+    generic_plat->system_reset(reset_type, reset_reason,
+             generic_plat_match);
+    return;
+  }
+
+  fdt_system_reset(reset_type, reset_reason);
+}
+
+#define EDK2_ROOT_FW_REGION       0
+#define EDK2_FW_REGION            1
+#define EDK2_VARIABLE_REGION    2
+#define EDK2_ALL_REGION            3
+#define EDK2_END_REGION            4
+static struct sbi_domain_memregion root_memregs[EDK2_END_REGION + 1] = { 0 };
+
+struct sbi_domain_memregion *get_mem_regions(void) {
+  /* EDK2 root firmware domain memory region */
+  root_memregs[EDK2_ROOT_FW_REGION].order = log2roundup(FixedPcdGet32(PcdRootFirmwareDomainSize));
+  root_memregs[EDK2_ROOT_FW_REGION].base = FixedPcdGet32(PcdRootFirmwareDomainBaseAddress);
+  root_memregs[EDK2_ROOT_FW_REGION].flags = 0;
+
+    /*EDK2 firmware domain memory region */
+  root_memregs[EDK2_FW_REGION].order = log2roundup(FixedPcdGet32(PcdFirmwareDomainSize));
+  root_memregs[EDK2_FW_REGION].base = FixedPcdGet32(PcdFirmwareDomainBaseAddress);
+  root_memregs[EDK2_FW_REGION].flags = SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREGION_READABLE;
+
+    /*EDK2 firmware domain memory region */
+  root_memregs[EDK2_VARIABLE_REGION].order = log2roundup(FixedPcdGet32(PcdVariableFirmwareRegionSize));
+  root_memregs[EDK2_VARIABLE_REGION].base = FixedPcdGet32(PcdVariableFirmwareRegionBaseAddress);
+  root_memregs[EDK2_VARIABLE_REGION].flags = SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGION_WRITEABLE;
+
+  /* EDK2 domain allow everything memory region */
+  root_memregs[EDK2_ALL_REGION].order = __riscv_xlen;
+  root_memregs[EDK2_ALL_REGION].base = 0;
+  root_memregs[EDK2_ALL_REGION].flags = (SBI_DOMAIN_MEMREGION_READABLE |
+            SBI_DOMAIN_MEMREGION_WRITEABLE |
+            SBI_DOMAIN_MEMREGION_EXECUTABLE);
+
+  /* EDK2 domain memory region end */
+  root_memregs[EDK2_END_REGION].order = 0;
+
+  return root_memregs;
+}
+
 const struct sbi_platform_operations platform_ops = {
-  .early_init    = generic_early_init,
-  .final_init    = generic_final_init,
-  .early_exit    = generic_early_exit,
-  .final_exit    = generic_final_exit,
-  .domains_init    = generic_domains_init,
-  .console_init    = fdt_serial_init,
-  .irqchip_init    = fdt_irqchip_init,
-  .irqchip_exit    = fdt_irqchip_exit,
-  .ipi_init    = fdt_ipi_init,
-  .ipi_exit    = fdt_ipi_exit,
+  .early_init            = generic_early_init,
+  .final_init            = generic_final_init,
+  .early_exit            = generic_early_exit,
+  .final_exit            = generic_final_exit,
+  .domains_root_regions  = get_mem_regions,
+  .domains_init          = generic_domains_init,
+  .console_init          = fdt_serial_init,
+  .irqchip_init          = fdt_irqchip_init,
+  .irqchip_exit          = fdt_irqchip_exit,
+  .ipi_init              = fdt_ipi_init,
+  .ipi_exit              = fdt_ipi_exit,
   .get_tlbr_flush_limit  = generic_tlbr_flush_limit,
-  .timer_init    = fdt_timer_init,
-  .timer_exit    = fdt_timer_exit,
+  .timer_init            = fdt_timer_init,
+  .timer_exit            = fdt_timer_exit,
 };
 
 #if FixedPcdGet32(PcdBootableHartNumber) == 4

+ 20 - 20
Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec

@@ -1,7 +1,7 @@
 ## @file  RiscVPlatformPkg.dec
 # This Package provides UEFI RISC-V platform modules and libraries.
 #
-# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -31,33 +31,33 @@
   gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize|0x0|UINT32|0x00001003
   gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|0x0|UINT32|0x00001004
   gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize|0x0|UINT32|0x00001005
-  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|0x0|UINT32|0x00001016
-  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvSize|0x0|UINT32|0x00001017
-
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|0x0|UINT32|0x00001006
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvSize|0x0|UINT32|0x00001007
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress|0x0|UINT32|0x00001008
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize|0x0|UINT32|0x00001009
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress|0x0|UINT32|0x0000100a
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize|0x0|UINT32|0x0000100b
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress|0x0|UINT32|0x0000100c
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize|0x0|UINT32|0x0000100d
 #
 # Definition of EFI Variable region
 #
-  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x00001010
-  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x00001011
-  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00001012
-  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|0|UINT32|0x00001013
-  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase|0|UINT32|0x00001014
-  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|0|UINT32|0x00001015
-#
-# Firmware region which is protected by PMP.
-#
-  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwBlockSize|0|UINT32|0x00001020
-  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress|0|UINT32|0x00001021
-  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress|0|UINT32|0x00001022
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x00001040
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x00001041
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00001042
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|0|UINT32|0x00001043
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase|0|UINT32|0x00001044
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|0|UINT32|0x00001045
+
 #
 # Definition of RISC-V Hart
 #
-  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001023
-  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001024
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001083
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001084
 #
 # The bootable hart core number, which is incorporate with OpenSBI platform hart_index2id value.
 #
-  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber|0|UINT32|0x00001025
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber|0|UINT32|0x00001085
 #
 # Definitions for OpenSbi
 #
@@ -73,7 +73,7 @@
 [PcdsPatchableInModule]
 
 [PcdsFeatureFlag]
-  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|0x00001006
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|0x00001200
 
 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
 

+ 3 - 4
Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020 , Hewlett Packard Enterprise Development LP. All rights reserved.
+ * Copyright (c) 2021 , Hewlett Packard Enterprise Development LP. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-2-Clause
  *
@@ -71,9 +71,8 @@ _scratch_init:
   /* Initialize scratch space */
 
   /* Firmware range and size */
-  li    a4, FixedPcdGet32 (PcdFwStartAddress)
-  li    a5, FixedPcdGet32 (PcdFwEndAddress)
-  sub   a5, a5, a4
+  li    a4, FixedPcdGet32 (PcdRootFirmwareDomainBaseAddress)
+  li    a5, FixedPcdGet32 (PcdRootFirmwareDomainSize)
   sd    a4, SBI_SCRATCH_FW_START_OFFSET(tp)
   sd    a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp)
 

+ 19 - 34
Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c

@@ -1,7 +1,7 @@
 /** @file
   RISC-V SEC phase module.
 
-  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+  Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -336,7 +336,7 @@ FindAndReportEntryPoints (
 
 **/
 VOID
-DebutPrintFirmwareContext (
+DebugPrintFirmwareContext (
     EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext
     )
 {
@@ -398,7 +398,7 @@ TemporaryRamMigration (
   //
   FirmwareContext->PeiServiceTable += (unsigned long)((UINTN)NewStack - (UINTN)OldStack);
   DEBUG ((DEBUG_INFO, "%a: OpenSBI Firmware Context is relocated to 0x%x\n", __FUNCTION__, FirmwareContext));
-  DebutPrintFirmwareContext ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)FirmwareContext);
+  DebugPrintFirmwareContext ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)FirmwareContext);
 
   register uintptr_t a0 asm ("a0") = (uintptr_t)((UINTN)NewStack - (UINTN)OldStack);
   asm volatile ("add sp, sp, a0"::"r"(a0):);
@@ -496,12 +496,12 @@ RegisterFirmwareSbiExtension (
   This function transits to S-mode PEI phase from M-mode SEC phase.
 
   @param[in]  BootHartId     Hardware thread ID of boot hart.
-  @param[in]  FuncArg1       Arg1 delivered from previous phase.
+  @param[in]  Scratch       Pointer to sbi_scratch structure.
 
 **/
 VOID EFIAPI PeiCore (
-  IN  UINTN  BootHartId,
-  IN  UINTN  FuncArg1
+  IN  UINTN BootHartId,
+  IN  struct sbi_scratch *Scratch
   )
 {
   EFI_SEC_PEI_HAND_OFF        SecCoreData;
@@ -529,7 +529,7 @@ VOID EFIAPI PeiCore (
   //
   DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FUNCTION__));
   for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
-    SbiGetMscratchHartid (HartId, &ScratchSpace);
+    ScratchSpace = sbi_hartid_to_scratch (HartId);
     if(ScratchSpace != NULL) {
       DEBUG((DEBUG_INFO, "          Hart %d: 0x%x\n", HartId, ScratchSpace));
     }
@@ -540,9 +540,8 @@ VOID EFIAPI PeiCore (
   // Firmware context residents in stack and will be switched to memory when
   // temporary RAM migration.
   //
-  SbiGetMscratchHartid (BootHartId, &ScratchSpace);
   ZeroMem ((VOID *)&FirmwareContext, sizeof (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT));
-  ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(ScratchSpace);
+  ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(Scratch);
   if (ThisSbiPlatform->opensbi_version > OPENSBI_VERSION) {
       DEBUG ((DEBUG_ERROR, "%a: OpenSBI platform table version 0x%x is newer than OpenSBI version 0x%x.\n"
                            "There maybe be some backward compatable issues.\n",
@@ -562,13 +561,13 @@ VOID EFIAPI PeiCore (
   //
   // Save Flattened Device tree in firmware context
   //
-  FirmwareContext.FlattenedDeviceTree = FuncArg1;
+  FirmwareContext.FlattenedDeviceTree = Scratch->next_arg1;
 
   //
   // Set firmware context Hart-specific pointer
   //
   for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
-    SbiGetMscratchHartid (HartId, &ScratchSpace);
+    ScratchSpace = sbi_hartid_to_scratch (HartId);
     if (ScratchSpace != NULL) {
       FirmwareContext.HartSpecific[HartId] =
         (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE);
@@ -588,6 +587,10 @@ VOID EFIAPI PeiCore (
   //
   // Transfer the control to the PEI core
   //
+  Scratch->next_addr = (UINTN)(*PeiCoreEntryPoint);
+  Scratch->next_mode = PRV_S;
+  DEBUG ((DEBUG_INFO, "%a: Initializing OpenSBI library for booting hart %d\n", __FUNCTION__, BootHartId));
+  sbi_init(Scratch);
   (*PeiCoreEntryPoint) (&SecCoreData, (EFI_PEI_PPI_DESCRIPTOR *)&mPrivateDispatchTable);
 }
 
@@ -598,34 +601,19 @@ VOID EFIAPI PeiCore (
   To register the SBI extension we stay in M-Mode and then transition here,
   rather than before in sbi_init.
 
-  @param[in]  ThisHartId     Hardware thread ID.
-  @param[in]  FuncArg1       Arg1 delivered from previous phase.
+  @param[in]  ThisHartId    Hardware thread ID.
+  @param[in]  Scratch       Pointer to sbi_scratch structure.
 
 **/
 VOID
 EFIAPI
 LaunchPeiCore (
   IN  UINTN  ThisHartId,
-  IN  UINTN  FuncArg1
+  IN  struct sbi_scratch *Scratch
   )
 {
-  UINT32 PeiCoreMode;
-
-  DEBUG ((DEBUG_INFO, "%a: Set boot hart done.\n", __FUNCTION__));
-  atomic_write (&BootHartDone, (UINT64)TRUE);
   RegisterFirmwareSbiExtension ();
-
-  PeiCoreMode = FixedPcdGet32 (PcdPeiCorePrivilegeMode);
-  if (PeiCoreMode == PRV_S) {
-    DEBUG ((DEBUG_INFO, "%a: Switch to S-Mode for PeiCore.\n", __FUNCTION__));
-    sbi_hart_switch_mode (ThisHartId, FuncArg1, (UINTN)PeiCore, PRV_S, FALSE);
-  } else if (PeiCoreMode == PRV_M) {
-    DEBUG ((DEBUG_INFO, "%a: Switch to M-Mode for PeiCore.\n", __FUNCTION__));
-    PeiCore (ThisHartId, FuncArg1);
-  } else {
-    DEBUG ((DEBUG_INFO, "%a: The privilege mode specified in PcdPeiCorePrivilegeMode is not supported.\n", __FUNCTION__));
-    while (TRUE);
-  }
+  PeiCore (ThisHartId, Scratch);
 }
 
 /**
@@ -750,10 +738,7 @@ VOID EFIAPI SecCoreStartUpWithStack(
   HartFirmwareContext->HartSwitchMode = RiscVOpenSbiHartSwitchMode;
 
   if (HartId == FixedPcdGet32(PcdBootHartId)) {
-    Scratch->next_addr = (UINTN)LaunchPeiCore;
-    Scratch->next_mode = PRV_M;
-    DEBUG ((DEBUG_INFO, "%a: Initializing OpenSBI library for booting hart %d\n", __FUNCTION__, HartId));
-    sbi_init(Scratch);
+    LaunchPeiCore (HartId, Scratch);
   }
 
   //

+ 3 - 3
Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf

@@ -1,7 +1,7 @@
 ## @file
 #  RISC-V SEC module.
 #
-#  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#  Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -64,8 +64,8 @@
   gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
   gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
   gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
-  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress
-  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize
   gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
   gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase
   gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize

+ 60 - 20
Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc

@@ -1,7 +1,7 @@
 ## @file
 #  Definitions of Flash definition file on SiFive Freedom U540 HiFive Unleashed RISC-V platform
 #
-#  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#  Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -10,37 +10,77 @@
 DEFINE BLOCK_SIZE        = 0x1000
 
 DEFINE FW_BASE_ADDRESS   = 0x80000000
-DEFINE FW_SIZE           = 0x00820000
-DEFINE FW_BLOCKS         = 0x820
+DEFINE FW_SIZE           = 0x00900000
+DEFINE FW_BLOCKS         = 0x900
 
 #
 # 0x000000-0x7DFFFF code
 # 0x7E0000-0x800000 variables
 #
 DEFINE CODE_BASE_ADDRESS = 0x80000000
-DEFINE CODE_SIZE         = 0x007E0000
-DEFINE CODE_BLOCKS       = 0x7E0
+DEFINE CODE_SIZE         = 0x00800000
+DEFINE CODE_BLOCKS       = 0x800
 DEFINE VARS_BLOCKS       = 0x20
 
-DEFINE SECFV_OFFSET      = 0x00000000
-DEFINE SECFV_SIZE        = 0x00030000
-DEFINE PEIFV_OFFSET      = 0x00030000
-DEFINE PEIFV_SIZE        = 0x00080000
-DEFINE SCRATCH_OFFSET    = 0x000b0000
-DEFINE SCRATCH_SIZE      = 0x00010000
-DEFINE FVMAIN_OFFSET     = 0x00100000 # Must be power of 2 for PMP setting
-DEFINE FVMAIN_SIZE       = 0x0018C000
-DEFINE VARS_OFFSET       = 0x007E0000
-DEFINE VARS_SIZE         = 0x00020000
-DEFINE DTB_OFFSET        = 0x00800000
-DEFINE DTB_SIZE          = 0x00002000
+#
+# SEC + opensbi library is the root FW domain.
+# The base address must be round up to log2.
+#
+DEFINE SECFV_OFFSET        = 0x00000000
+DEFINE SECFV_SIZE          = 0x00040000
+DEFINE ROOT_FW_DOMAIN_SIZE = $(SECFV_SIZE)
+
+#
+# Other FV regions are in the second FW domain.
+# The size of memory region must be power of 2.
+# The base address must be aligned with the size.
+#
+# FW memory region
+#
+DEFINE PEIFV_OFFSET                  = 0x00400000
+DEFINE PEIFV_SIZE                    = 0x00180000
+DEFINE FVMAIN_OFFSET                 = 0x00580000
+DEFINE FVMAIN_SIZE                   = 0x00280000
+
+#
+# EFI Variable memory region.
+# The total size of EFI Variable FD must include
+# all of sub regions of EFI Variable
+#
+DEFINE VARS_OFFSET                   = 0x00800000
+DEFINE VARS_SIZE                     = 0x00007000
+DEFINE VARS_FTW_WORKING_OFFSET       = 0x00807000
+DEFINE VARS_FTW_WORKING_SIZE         = 0x00001000
+DEFINE VARS_FTW_SPARE_OFFSET         = 0x00808000
+DEFINE VARS_FTW_SPARE_SIZE           = 0x00018000
+
+#
+# Device Tree memory region
+#
+DEFINE DTB_OFFSET                    = 0x00840000
+DEFINE DTB_SIZE                      = 0x00002000
+
+#
+# Scratch area memory region
+#
+DEFINE SCRATCH_OFFSET                = 0x00880000
+DEFINE SCRATCH_SIZE                  = 0x00010000
+
+
+DEFINE FW_DOMAIN_SIZE    = $(FVMAIN_OFFSET) + $(FVMAIN_SIZE) - $(PEIFV_OFFSET)
+DEFINE VARIABLE_FW_SIZE  = $(VARS_FTW_SPARE_OFFSET) + $(VARS_FTW_SPARE_SIZE) - $(VARS_OFFSET)
+
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress = $(CODE_BASE_ADDRESS) + $(SECFV_OFFSET)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize        = $(ROOT_FW_DOMAIN_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress     = $(CODE_BASE_ADDRESS) + $(PEIFV_OFFSET)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize            = $(FW_DOMAIN_SIZE)
 
 SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress = $(FW_BASE_ADDRESS) + $(VARS_OFFSET)
-SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize        = $(VARS_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize        = $(VARS_SIZE) + $(VARS_FTW_WORKING_SIZE) + $(VARS_FTW_SPARE_SIZE)
 SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize   = $(BLOCK_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress = $(CODE_BASE_ADDRESS) + $(VARS_OFFSET)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize        = $(VARIABLE_FW_SIZE)
 
-SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress   = $(CODE_BASE_ADDRESS)
-SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress     = $(CODE_BASE_ADDRESS) + $(SECFV_SIZE) + $(PEIFV_SIZE) + $(SCRATCH_SIZE) + $(DTB_SIZE)
 SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize = 8192
 SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase   = $(CODE_BASE_ADDRESS) + $(SCRATCH_OFFSET)
 SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize   = $(SCRATCH_SIZE)

+ 4 - 4
Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/VarStore.fdf.inc

@@ -1,7 +1,7 @@
 ## @file
 #  FDF include file with Layout Regions that define an empty variable store.
 #
-#  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#  Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 #  Copyright (C) 2014, Red Hat, Inc.
 #  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
 #
@@ -9,7 +9,7 @@
 #
 ##
 
-$(VARS_OFFSET)|0x00007000
+$(VARS_OFFSET)|$(VARS_SIZE)
 gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
 #
 # NV_VARIABLE_STORE
@@ -56,7 +56,7 @@ DATA = {
   0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 }
 
-0x007e7000|0x00001000
+$(VARS_FTW_WORKING_OFFSET)|$(VARS_FTW_WORKING_SIZE)
 gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
 #
 #NV_FTW_WROK
@@ -72,7 +72,7 @@ DATA = {
   0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 }
 
-0x007e8000|0x00018000
+$(VARS_FTW_SPARE_OFFSET)|$(VARS_FTW_SPARE_SIZE)
 gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
 #
 #NV_FTW_SPARE