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@@ -12,6 +12,10 @@
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#define NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS 0x1E00000
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#define NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS 0x1E00000
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+#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE)
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+#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
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+#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
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+
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/**
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/**
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The Device Configuration Unit provides general purpose configuration and
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The Device Configuration Unit provides general purpose configuration and
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status for the device. These registers only support 32-bit accesses.
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status for the device. These registers only support 32-bit accesses.
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