Chassis.h 1.3 KB

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  1. /** @file
  2. Copyright 2018-2020 NXP
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #ifndef CHASSIS_H__
  6. #define CHASSIS_H__
  7. #include <Uefi.h>
  8. #define NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS 0x1E00000
  9. #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE)
  10. #define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
  11. #define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
  12. /**
  13. The Device Configuration Unit provides general purpose configuration and
  14. status for the device. These registers only support 32-bit accesses.
  15. **/
  16. #pragma pack(1)
  17. typedef struct {
  18. UINT8 Reserved0[0x70 - 0x0];
  19. UINT32 DeviceDisableRegister1; // Device Disable Register 1
  20. UINT32 DeviceDisableRegister2; // Device Disable Register 2
  21. UINT32 DeviceDisableRegister3; // Device Disable Register 3
  22. UINT32 DeviceDisableRegister4; // Device Disable Register 4
  23. UINT32 DeviceDisableRegister5; // Device Disable Register 5
  24. UINT32 DeviceDisableRegister6; // Device Disable Register 6
  25. UINT32 DeviceDisableRegister7; // Device Disable Register 7
  26. UINT8 Reserved1[0xa4 - 0x8c];
  27. UINT32 Svr; // System Version Register
  28. UINT8 Reserved2[0x100 - 0xa8];
  29. UINT32 RcwSr[32]; // Reset Control Word Status Register
  30. } NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG;
  31. #pragma pack()
  32. #endif // CHASSIS_H__