dw_mmc.c 11 KB

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  1. /*
  2. * (C) Copyright 2012 SAMSUNG Electronics
  3. * Jaehoon Chung <jh80.chung@samsung.com>
  4. * Rajeshawari Shinde <rajeshwari.s@samsung.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <bouncebuf.h>
  9. #include <comdef.h>
  10. #include <mmc.h>
  11. #include <dwmmc.h>
  12. #include <timer.h>
  13. #include "errno.h"
  14. #define PAGE_SIZE 4096
  15. static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
  16. {
  17. unsigned long timeout = 1000;
  18. u32 ctrl;
  19. dwmci_writel(host, DWMCI_CTRL, value);
  20. while (timeout--) {
  21. ctrl = dwmci_readl(host, DWMCI_CTRL);
  22. if (!(ctrl & DWMCI_RESET_ALL))
  23. return 1;
  24. }
  25. return 0;
  26. }
  27. static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
  28. u32 desc0, u32 desc1, u32 desc2)
  29. {
  30. struct dwmci_idmac *desc = idmac;
  31. desc->flags = desc0;
  32. desc->cnt = desc1;
  33. desc->addr = desc2;
  34. desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac);
  35. }
  36. static void dwmci_prepare_data(struct dwmci_host *host,
  37. struct mmc_data *data,
  38. struct dwmci_idmac *cur_idmac,
  39. void *bounce_buffer)
  40. {
  41. unsigned long ctrl;
  42. unsigned int i = 0, flags, cnt, blk_cnt;
  43. unsigned int data_start, data_end;
  44. blk_cnt = data->blocks;
  45. dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
  46. data_start = (unsigned int)cur_idmac;
  47. dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac);
  48. do {
  49. flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
  50. flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
  51. if (blk_cnt <= 8) {
  52. flags |= DWMCI_IDMAC_LD;
  53. cnt = data->blocksize * blk_cnt;
  54. } else
  55. cnt = data->blocksize * 8;
  56. dwmci_set_idma_desc(cur_idmac, flags, cnt,
  57. (unsigned int)bounce_buffer + (i * PAGE_SIZE));
  58. if (blk_cnt <= 8)
  59. break;
  60. blk_cnt -= 8;
  61. cur_idmac++;
  62. i++;
  63. } while(1);
  64. data_end = (unsigned int)cur_idmac;
  65. //flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
  66. ctrl = dwmci_readl(host, DWMCI_CTRL);
  67. ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
  68. dwmci_writel(host, DWMCI_CTRL, ctrl);
  69. ctrl = dwmci_readl(host, DWMCI_BMOD);
  70. ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
  71. //ctrl |= DWMCI_BMOD_IDMAC_EN;
  72. dwmci_writel(host, DWMCI_BMOD, ctrl);
  73. dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
  74. dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
  75. }
  76. static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
  77. {
  78. int ret = 0;
  79. u32 timeout = 40000000;
  80. u32 mask=0, size, i, len = 0;
  81. u32 *buf = NULL;
  82. unsigned int start = get_timer(0);
  83. u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
  84. RX_WMARK_SHIFT) + 1) * 2;
  85. size = data->blocksize * data->blocks / 4;
  86. if (data->flags == MMC_DATA_READ)
  87. buf = (unsigned int *)data->dest;
  88. else
  89. buf = (unsigned int *)data->src;
  90. for (;;) {
  91. mask = dwmci_readl(host, DWMCI_RINTSTS);
  92. /* Error during data transfer. */
  93. if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
  94. printk("%s: DATA ERROR! mask:0x%x 0x%x\r\n", __func__,mask,(DWMCI_DATA_ERR | DWMCI_DATA_TOUT));
  95. ret = -EINVAL;
  96. break;
  97. }
  98. if (host->fifo_mode && size) {
  99. len = 0;
  100. if (data->flags == MMC_DATA_READ &&
  101. (mask & DWMCI_INTMSK_RXDR)) {
  102. while (size) {
  103. len = dwmci_readl(host, DWMCI_STATUS);
  104. len = (len >> DWMCI_FIFO_SHIFT) &
  105. DWMCI_FIFO_MASK;
  106. len = min(size, len);
  107. for (i = 0; i < len; i++)
  108. *buf++ =
  109. dwmci_readl(host, DWMCI_DATA);
  110. size = size > len ? (size - len) : 0;
  111. }
  112. dwmci_writel(host, DWMCI_RINTSTS,
  113. DWMCI_INTMSK_RXDR);
  114. } else if (data->flags == MMC_DATA_WRITE &&
  115. (mask & DWMCI_INTMSK_TXDR)) {
  116. while (size) {
  117. len = dwmci_readl(host, DWMCI_STATUS);
  118. len = fifo_depth - ((len >>
  119. DWMCI_FIFO_SHIFT) &
  120. DWMCI_FIFO_MASK);
  121. len = min(size, len);
  122. for (i = 0; i < len; i++)
  123. dwmci_writel(host, DWMCI_DATA,
  124. *buf++);
  125. size = size > len ? (size - len) : 0;
  126. }
  127. dwmci_writel(host, DWMCI_RINTSTS,
  128. DWMCI_INTMSK_TXDR);
  129. }
  130. }
  131. /* Data arrived correctly. */
  132. if (mask & DWMCI_INTMSK_DTO) {
  133. ret = 0;
  134. break;
  135. }
  136. /* Check for timeout. */
  137. if (get_timer(start) > timeout) {
  138. printk("%s: Timeout waiting for data!\n",__func__);
  139. ret = -ETIMEDOUT;
  140. break;
  141. }
  142. }
  143. dwmci_writel(host, DWMCI_RINTSTS, mask);
  144. return ret;
  145. }
  146. static int dwmci_set_transfer_mode(struct dwmci_host *host,
  147. struct mmc_data *data)
  148. {
  149. unsigned long mode;
  150. mode = DWMCI_CMD_DATA_EXP;
  151. if (data->flags & MMC_DATA_WRITE)
  152. mode |= DWMCI_CMD_RW;
  153. return mode;
  154. }
  155. static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  156. struct mmc_data *data)
  157. {
  158. struct dwmci_host *host = mmc->priv;
  159. ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
  160. data ? DIV_ROUND_UP(data->blocks, 8) : 0);
  161. int ret = 0, flags = 0, i;
  162. unsigned int timeout = 100000;
  163. u32 retry = 10000;
  164. u32 mask, ctrl;
  165. unsigned int start = get_timer(0);
  166. struct bounce_buffer bbstate;
  167. while ((dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY)) {
  168. if (get_timer(start) > timeout) {
  169. printk("%s: Timeout on data busy\r\n", __func__);
  170. return -ETIMEDOUT;
  171. }
  172. }
  173. dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
  174. if (data) {
  175. if (host->fifo_mode) {
  176. dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
  177. dwmci_writel(host, DWMCI_BYTCNT,
  178. data->blocksize * data->blocks);
  179. dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
  180. } else {
  181. if (data->flags == MMC_DATA_READ) {
  182. bounce_buffer_start(&bbstate, (void*)data->dest,
  183. data->blocksize *
  184. data->blocks, GEN_BB_WRITE);
  185. } else {
  186. bounce_buffer_start(&bbstate, (void*)data->src,
  187. data->blocksize *
  188. data->blocks, GEN_BB_READ);
  189. }
  190. dwmci_prepare_data(host, data, cur_idmac,
  191. bbstate.bounce_buffer);
  192. }
  193. }
  194. dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
  195. if (data)
  196. flags = dwmci_set_transfer_mode(host, data);
  197. if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
  198. return -1;
  199. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  200. flags |= DWMCI_CMD_ABORT_STOP;
  201. else
  202. flags |= DWMCI_CMD_PRV_DAT_WAIT;
  203. if (cmd->resp_type & MMC_RSP_PRESENT) {
  204. flags |= DWMCI_CMD_RESP_EXP;
  205. if (cmd->resp_type & MMC_RSP_136)
  206. flags |= DWMCI_CMD_RESP_LENGTH;
  207. }
  208. if (cmd->resp_type & MMC_RSP_CRC)
  209. flags |= DWMCI_CMD_CHECK_CRC;
  210. flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
  211. // printk("Sending CMD%d\r\n",cmd->cmdidx);
  212. dwmci_writel(host, DWMCI_CMD, flags);
  213. for (i = 0; i < retry; i++) {
  214. mask = dwmci_readl(host, DWMCI_RINTSTS);
  215. if (mask & DWMCI_INTMSK_CDONE) {
  216. if (!data)
  217. dwmci_writel(host, DWMCI_RINTSTS, mask);
  218. break;
  219. }
  220. }
  221. if (i == retry) {
  222. printk("%s: Timeout.\r\n", __func__);
  223. return -ETIMEDOUT;
  224. }
  225. if (mask & DWMCI_INTMSK_RTO) {
  226. /*
  227. * Timeout here is not necessarily fatal. (e)MMC cards
  228. * will splat here when they receive CMD55 as they do
  229. * not support this command and that is exactly the way
  230. * to tell them apart from SD cards. Thus, this output
  231. * below shall be printf(). eMMC cards also do not favor
  232. * CMD8, please keep that in mind.
  233. */
  234. printk("%s: Response Timeout.\r\n", __func__);
  235. return -ETIMEDOUT;
  236. } else if (mask & DWMCI_INTMSK_RE) {
  237. printk("%s: Response Error.\r\n", __func__);
  238. return -EIO;
  239. }
  240. if (cmd->resp_type & MMC_RSP_PRESENT) {
  241. if (cmd->resp_type & MMC_RSP_136) {
  242. cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
  243. cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
  244. cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
  245. cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
  246. } else {
  247. cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
  248. }
  249. }
  250. if (data) {
  251. ret = dwmci_data_transfer(host, data);
  252. /* only dma mode need it */
  253. if (!host->fifo_mode) {
  254. ctrl = dwmci_readl(host, DWMCI_CTRL);
  255. ctrl &= ~(DWMCI_DMA_EN);
  256. dwmci_writel(host, DWMCI_CTRL, ctrl);
  257. // bounce_buffer_stop(&bbstate);
  258. }
  259. }
  260. return ret;
  261. }
  262. static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
  263. {
  264. u32 div, status;
  265. int timeout = 10000;
  266. unsigned long sclk;
  267. if ((freq == host->clock) || (freq == 0))
  268. return 0;
  269. /*
  270. * If host->get_mmc_clk isn't defined,
  271. * then assume that host->bus_hz is source clock value.
  272. * host->bus_hz should be set by user.
  273. */
  274. if (host->get_mmc_clk)
  275. sclk = host->get_mmc_clk(host, freq);
  276. else if (host->bus_hz)
  277. sclk = host->bus_hz;
  278. else {
  279. //printf("%s: Didn't get source clock value.\r\n", __func__);
  280. return -EINVAL;
  281. }
  282. if (sclk == freq)
  283. div = 0; /* bypass mode */
  284. else
  285. div = DIV_ROUND_UP(sclk, 2 * freq);
  286. dwmci_writel(host, DWMCI_CLKENA, 0);
  287. dwmci_writel(host, DWMCI_CLKSRC, 0);
  288. dwmci_writel(host, DWMCI_CLKDIV, div);
  289. dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
  290. DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
  291. do {
  292. status = dwmci_readl(host, DWMCI_CMD);
  293. if (timeout-- < 0) {
  294. //printf("%s: Timeout!\n", __func__);
  295. return -ETIMEDOUT;
  296. }
  297. } while (status & DWMCI_CMD_START);
  298. dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
  299. DWMCI_CLKEN_LOW_PWR);
  300. dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
  301. DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
  302. timeout = 10000;
  303. do {
  304. status = dwmci_readl(host, DWMCI_CMD);
  305. if (timeout-- < 0) {
  306. //printf("%s: Timeout!\r\n", __func__);
  307. return -ETIMEDOUT;
  308. }
  309. } while (status & DWMCI_CMD_START);
  310. host->clock = freq;
  311. return 0;
  312. }
  313. static void dwmci_set_ios(struct mmc *mmc)
  314. {
  315. struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
  316. u32 ctype, regs;
  317. dwmci_setup_bus(host, mmc->clock);
  318. switch (mmc->bus_width) {
  319. case 8:
  320. ctype = DWMCI_CTYPE_8BIT;
  321. break;
  322. case 4:
  323. ctype = DWMCI_CTYPE_4BIT;
  324. break;
  325. default:
  326. ctype = DWMCI_CTYPE_1BIT;
  327. break;
  328. }
  329. dwmci_writel(host, DWMCI_CTYPE, ctype);
  330. regs = dwmci_readl(host, DWMCI_UHS_REG);
  331. if (mmc->ddr_mode)
  332. regs |= DWMCI_DDR_MODE;
  333. else
  334. regs &= ~DWMCI_DDR_MODE;
  335. dwmci_writel(host, DWMCI_UHS_REG, regs);
  336. if (host->clksel)
  337. host->clksel(host);
  338. }
  339. static int dwmci_init(struct mmc *mmc)
  340. {
  341. struct dwmci_host *host = mmc->priv;
  342. if (host->board_init)
  343. host->board_init(host);
  344. dwmci_writel(host, DWMCI_PWREN, 1);
  345. udelay(100);
  346. if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
  347. printk("%s[%d] Fail-reset!!\n", __func__, __LINE__);
  348. return -EIO;
  349. }
  350. /* Enumerate at 400KHz */
  351. dwmci_setup_bus(host, mmc->cfg->f_min);
  352. dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
  353. dwmci_writel(host, DWMCI_INTMASK, 0);
  354. dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
  355. dwmci_writel(host, DWMCI_IDINTEN, 0);
  356. dwmci_writel(host, DWMCI_BMOD, 1);
  357. if (!host->fifoth_val) {
  358. unsigned int fifo_size;
  359. fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
  360. fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
  361. host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
  362. TX_WMARK(fifo_size / 2);
  363. }
  364. dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
  365. dwmci_writel(host, DWMCI_CLKENA, 0);
  366. dwmci_writel(host, DWMCI_CLKSRC, 0);
  367. return 0;
  368. }
  369. static const struct mmc_ops dwmci_ops = {
  370. .send_cmd = dwmci_send_cmd,
  371. .set_ios = dwmci_set_ios,
  372. .init = dwmci_init,
  373. };
  374. int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk,u32 dev_num)
  375. {
  376. host->cfg.name = host->name;
  377. host->cfg.ops = &dwmci_ops;
  378. host->cfg.f_min = min_clk;
  379. host->cfg.f_max = max_clk;
  380. host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  381. host->cfg.host_caps = host->caps;
  382. if (host->buswidth == 8) {
  383. host->cfg.host_caps |= MMC_MODE_8BIT;
  384. host->cfg.host_caps &= ~MMC_MODE_4BIT;
  385. } else {
  386. host->cfg.host_caps |= MMC_MODE_4BIT;
  387. host->cfg.host_caps &= ~MMC_MODE_8BIT;
  388. }
  389. host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
  390. host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  391. host->mmc = mmc_create(&host->cfg, host, dev_num);
  392. if (host->mmc == NULL)
  393. return -1;
  394. return 0;
  395. }