mach-cybook_orizon.c 7.6 KB

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  1. /* linux/arch/arm/mach-s3c2416/mach-cybook_orizon.c
  2. *
  3. * Slightly based on mach-s3c2416.c
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/types.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/list.h>
  14. #include <linux/timer.h>
  15. #include <linux/init.h>
  16. #include <linux/serial_core.h>
  17. #include <linux/platform_device.h>
  18. #include <asm/mach/arch.h>
  19. #include <asm/mach/map.h>
  20. #include <asm/mach/irq.h>
  21. #include <asm/setup.h>
  22. #include <asm/hardware.h>
  23. #include <asm/io.h>
  24. #include <asm/irq.h>
  25. #include <asm/mach-types.h>
  26. #include <asm/arch/regs-serial.h>
  27. #include <asm/arch/regs-gpio.h>
  28. #include <asm/arch/regs-gpioj.h>
  29. #include <asm/arch/regs-lcd.h>
  30. #include <asm/arch/regs-mem.h>
  31. #include <asm/arch/idle.h>
  32. #include <asm/arch/fb.h>
  33. #include <asm/plat-s3c24xx/s3c2410.h>
  34. #include <asm/plat-s3c24xx/s3c2440.h>
  35. #include <asm/plat-s3c24xx/clock.h>
  36. #include <asm/plat-s3c24xx/devs.h>
  37. #include <asm/plat-s3c24xx/cpu.h>
  38. #include <asm/plat-s3c24xx/common-smdk.h>
  39. #include <asm/arch/nand.h>
  40. #include <linux/mtd/mtd.h>
  41. #include <linux/mtd/partitions.h>
  42. #include <asm/arch/hsmmc.h>
  43. #include <cybook.h>
  44. unsigned int platform_type = CYBOOK_GEN4;
  45. unsigned long platform_capability = PLAT_CAP_GTILT | PLAT_CAP_SOUNDNO
  46. | PLAT_CAP_VTCON | PLAT_CAP_ORIZONFORM;
  47. static struct map_desc bkorizon_iodesc[] __initdata = {
  48. };
  49. #define UCON S3C2410_UCON_DEFAULT | S3C2440_UCON_FCLK
  50. #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  51. #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  52. static struct s3c24xx_uart_clksrc bkorizon_serial_clocks[] = {
  53. [0] = {
  54. .name = "pclk",
  55. .divisor = 1,
  56. .min_baud = 0,
  57. .max_baud = 0,
  58. },
  59. [1] = {
  60. .name = "esysclk",
  61. .divisor = 1,
  62. .min_baud = 0,
  63. .max_baud = 0,
  64. }
  65. };
  66. static struct s3c2410_uartcfg bkorizon_uartcfgs[] __initdata = {
  67. [0] = {
  68. .hwport = 0,
  69. .flags = 0,
  70. .ucon = 0x3c5,
  71. .ulcon = 0x03,
  72. .ufcon = 0x51,
  73. },
  74. [1] = { /* VRFY: Used by BT? */
  75. .hwport = 1,
  76. .flags = 0,
  77. /* Use PCLK */
  78. .ucon = 0x3c5,
  79. .ulcon = 0x03,
  80. .ufcon = 0x51,
  81. .clocks = bkorizon_serial_clocks,
  82. .clocks_size = ARRAY_SIZE(bkorizon_serial_clocks),
  83. },
  84. /* IR port */
  85. [2] = {
  86. .hwport = 2,
  87. .flags = 0,
  88. .ucon = 0x3c5,
  89. .ulcon = 0x03,
  90. .ufcon = 0x51,
  91. .clocks = bkorizon_serial_clocks,
  92. .clocks_size = ARRAY_SIZE(bkorizon_serial_clocks),
  93. }
  94. };
  95. extern struct platform_device orizon_device_cyio;
  96. extern struct platform_device orizon_device_tcon;
  97. /*** TODO: Verify this list and remove anything unneeded */
  98. static struct platform_device *bkorizon_devices[] __initdata = {
  99. &s3c_device_spi0,
  100. &s3c_device_spi1,
  101. &s3c_device_wdt,
  102. &s3c_device_i2c,
  103. &s3c_device_lcd,
  104. &s3c_device_rtc,
  105. &s3c_device_adc,
  106. &s3c_device_iis,
  107. &s3c_device_usbgadget,
  108. &s3c_device_usb,
  109. &s3c_device_hsmmc0,
  110. &s3c_device_hsmmc1,
  111. &s3c_device_ts_iic,
  112. &orizon_device_cyio,
  113. &orizon_device_tcon,
  114. };
  115. static struct s3c24xx_board bkorizon_board __initdata = {
  116. .devices = bkorizon_devices,
  117. .devices_count = ARRAY_SIZE(bkorizon_devices)
  118. };
  119. static void bkorizon_power_off(void)
  120. {
  121. printk(KERN_ERR "Will Shutdown...\n");
  122. s3c2410_gpio_cfgpin(S3C2410_GPD14, S3C2410_GPD14_OUTP);
  123. s3c2410_gpio_setpin(S3C2410_GPD14, 0);
  124. }
  125. static void __init bkorizon_map_io(void)
  126. {
  127. s3c24xx_init_io(bkorizon_iodesc, ARRAY_SIZE(bkorizon_iodesc));
  128. s3c24xx_init_clocks(12000000);
  129. s3c24xx_init_uarts(bkorizon_uartcfgs, ARRAY_SIZE(bkorizon_uartcfgs));
  130. s3c24xx_set_board(&bkorizon_board);
  131. }
  132. static void __init bkorizon_machine_init(void)
  133. {
  134. smdk_machine_init();
  135. pm_power_off = bkorizon_power_off;
  136. }
  137. static void __init bkorizon_fixup (struct machine_desc *desc, struct tag *tags,
  138. char **cmdline, struct meminfo *mi)
  139. {
  140. /*
  141. * Bank start addresses are not present in the information
  142. * passed in from the boot loader. We could potentially
  143. * detect them, but instead we hard-code them.
  144. */
  145. mi->bank[0].start = 0x30000000;
  146. mi->bank[0].size = 128*1024*1024;
  147. mi->bank[0].node = 0;
  148. mi->nr_banks = 1;
  149. }
  150. MACHINE_START(CYBOOK_ORIZON, "Cybook Orizon")
  151. /* Maintainer: Manoel Trapier <mtrapier@bookeen.com> */
  152. .phys_io = S3C2410_PA_UART,
  153. .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
  154. .boot_params = S3C2410_SDRAM_PA + 0x100,
  155. .init_irq = s3c24xx_init_irq,
  156. .map_io = bkorizon_map_io,
  157. .fixup = bkorizon_fixup,
  158. .init_machine = bkorizon_machine_init,
  159. .timer = &s3c24xx_timer,
  160. MACHINE_END
  161. /*
  162. * HS-MMC GPIO Set function for S3C2416 SMDK board
  163. */
  164. void hsmmc_set_gpio (uint channel, uint width)
  165. {
  166. switch (channel) {
  167. /* can supports 1 and 4 bit bus */
  168. case 0:
  169. /* GPIO E : Command, Clock */
  170. s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2450_GPE5_SD0_CLK);
  171. s3c2410_gpio_cfgpin(S3C2410_GPE6, S3C2450_GPE6_SD0_CMD);
  172. if (width == 1) {
  173. /* GPIO E : MMC DATA0[0] */
  174. s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2450_GPE7_SD0_DAT0);
  175. }
  176. else if (width == 4) {
  177. /* GPIO E : MMC DATA0[0:3] */
  178. s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2450_GPE7_SD0_DAT0);
  179. s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2450_GPE8_SD0_DAT1);
  180. s3c2410_gpio_cfgpin(S3C2410_GPE9, S3C2450_GPE9_SD0_DAT2);
  181. s3c2410_gpio_cfgpin(S3C2410_GPE10, S3C2450_GPE10_SD0_DAT3);
  182. }
  183. break;
  184. /* can supports 1 and 4 bit bus */
  185. case 1:
  186. /* GPIO L : Command, Clock */
  187. s3c2410_gpio_cfgpin(S3C2443_GPL8, S3C2450_GPL8_SD1CMD);
  188. s3c2410_gpio_cfgpin(S3C2443_GPL9, S3C2450_GPL9_SD1CLK);
  189. if (width == 1) {
  190. /* GPIO L : MMC DATA1[0] */
  191. s3c2410_gpio_cfgpin(S3C2443_GPL0, S3C2450_GPL0_SD1DAT0);
  192. }
  193. else if (width == 4) {
  194. /* GPIO L : MMC DATA1[0:3] */
  195. s3c2410_gpio_cfgpin(S3C2443_GPL0, S3C2450_GPL0_SD1DAT0);
  196. s3c2410_gpio_cfgpin(S3C2443_GPL1, S3C2450_GPL1_SD1DAT1);
  197. s3c2410_gpio_cfgpin(S3C2443_GPL2, S3C2450_GPL2_SD1DAT2);
  198. s3c2410_gpio_cfgpin(S3C2443_GPL3, S3C2450_GPL3_SD1DAT3);
  199. }
  200. break;
  201. default:
  202. break;
  203. }
  204. }
  205. EXPORT_SYMBOL_GPL(hsmmc_set_gpio);
  206. #define HOST_CAPS (MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | \
  207. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED)
  208. /* Channel 0 : added HS-MMC channel */
  209. struct s3c_hsmmc_cfg s3c_hsmmc0_platform = {
  210. .hwport = 0,
  211. .enabled = 1,
  212. .host_caps = 0xF ,
  213. .bus_width = 4,
  214. .highspeed = 0,
  215. /* ctrl for mmc */
  216. .fd_ctrl[MMC_MODE_MMC] = {
  217. .ctrl2 = 0xC0000100, /* ctrl2 for mmc */
  218. .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
  219. .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
  220. .ctrl4 = 0x3,
  221. },
  222. /* ctrl for sd */
  223. .fd_ctrl[MMC_MODE_SD] = {
  224. .ctrl2 = 0xC0000100, /* ctrl2 for sd */
  225. .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
  226. .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
  227. .ctrl4 = 0x3,
  228. },
  229. .clk_name[0] = "hsmmc", /* 1st clock source */
  230. .clk_name[1] = "esysclk", /* 2nd clock source hsmmc-epll by Ben Dooks */
  231. .clk_name[2] = "hsmmc-ext", /* 3rd clock source */
  232. };
  233. /* Channel 1 : default HS-MMC channel */
  234. struct s3c_hsmmc_cfg s3c_hsmmc1_platform = {
  235. .hwport = 1,
  236. .enabled = 1,
  237. .host_caps = 0xF ,
  238. .bus_width = 8,
  239. .highspeed = 0,
  240. /* ctrl for mmc */
  241. .fd_ctrl[MMC_MODE_MMC] = {
  242. .ctrl2 = 0xC0000100, /* ctrl2 for mmc */
  243. .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
  244. .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
  245. .ctrl4 = 0x3,
  246. },
  247. /* ctrl for sd */
  248. .fd_ctrl[MMC_MODE_SD] = {
  249. .ctrl2 = 0xC0000100, /* ctrl2 for sd */
  250. .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
  251. .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
  252. .ctrl4 = 0x3,
  253. },
  254. .clk_name[0] = "hsmmc", /* 1st clock source */
  255. .clk_name[1] = "esysclk", /* 2nd clock source hsmmc-epll by Ben Dooks */
  256. .clk_name[2] = "hsmmc-ext", /* 3rd clock source */
  257. };