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@@ -6,6 +6,16 @@
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All transactions for sending and receiving are most-significant-bit first and least-significant last.
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All transactions for sending and receiving are most-significant-bit first and least-significant last.
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For technical details of the underlying hardware refer to [metalphreak's ESP8266 HSPI articles](http://d.av.id.au/blog/tag/hspi/).
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For technical details of the underlying hardware refer to [metalphreak's ESP8266 HSPI articles](http://d.av.id.au/blog/tag/hspi/).
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+## A note on the SPI busses
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+
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+The ESP hardware provides two SPI busses, with IDs 0, and 1, which map to pins
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+generally labelled SPI and HSPI.
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+
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+If you are using any kind of development board which provides flash, then bus
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+ID 0 (SPI) is almost certainly used for communicating with the flash chip.
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+You probably want to choose bus ID 1 (HSPI) for your communication, as you
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+will have uncontended use of it.
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+
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## High Level Functions
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## High Level Functions
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The high level functions provide a send & receive API for half- and
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The high level functions provide a send & receive API for half- and
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full-duplex mode. Sent and received data items are restricted to 1 - 32 bit
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full-duplex mode. Sent and received data items are restricted to 1 - 32 bit
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