|
@@ -19,58 +19,67 @@
|
|
|
//
|
|
|
//////////////////////////////////////////////////////////////////////////////////
|
|
|
module main(
|
|
|
- /* input clock */
|
|
|
- input CLKIN,
|
|
|
-
|
|
|
- /* SNES signals */
|
|
|
- input [23:0] SNES_ADDR,
|
|
|
- input SNES_READ,
|
|
|
- input SNES_WRITE,
|
|
|
- input SNES_CS,
|
|
|
- inout [7:0] SNES_DATA,
|
|
|
- input SNES_CPU_CLK,
|
|
|
- input SNES_REFRESH,
|
|
|
- inout SNES_IRQ,
|
|
|
- output SNES_DATABUS_OE,
|
|
|
- output SNES_DATABUS_DIR,
|
|
|
- output IRQ_DIR,
|
|
|
- input SNES_SYSCLK,
|
|
|
-
|
|
|
- /* SRAM signals */
|
|
|
- inout [15:0] ROM_DATA,
|
|
|
- output [22:0] ROM_ADDR,
|
|
|
- output ROM_CE,
|
|
|
- output ROM_OE,
|
|
|
- output ROM_WE,
|
|
|
- output ROM_BHE,
|
|
|
- output ROM_BLE,
|
|
|
-
|
|
|
- /* MCU signals */
|
|
|
- input SPI_MOSI,
|
|
|
- inout SPI_MISO,
|
|
|
- input SPI_SS,
|
|
|
- inout SPI_SCK,
|
|
|
- input MCU_OVR,
|
|
|
-
|
|
|
- output DAC_MCLK,
|
|
|
- output DAC_LRCK,
|
|
|
- output DAC_SDOUT,
|
|
|
-
|
|
|
- /* SD signals */
|
|
|
- input [3:0] SD_DAT,
|
|
|
- inout SD_CMD,
|
|
|
- inout SD_CLK
|
|
|
-
|
|
|
- /* debug */
|
|
|
- //output DCM_IN_STOPPED,
|
|
|
- //output DCM_FX_STOPPED
|
|
|
- //input DCM_RST
|
|
|
- );
|
|
|
-
|
|
|
+ /* input clock */
|
|
|
+ input CLKIN,
|
|
|
+
|
|
|
+ /* SNES signals */
|
|
|
+ input [23:0] SNES_ADDR,
|
|
|
+ input SNES_READ,
|
|
|
+ input SNES_WRITE,
|
|
|
+ input SNES_CS,
|
|
|
+ inout [7:0] SNES_DATA,
|
|
|
+ input SNES_CPU_CLK,
|
|
|
+ input SNES_REFRESH,
|
|
|
+ output SNES_IRQ,
|
|
|
+ output SNES_DATABUS_OE,
|
|
|
+ output SNES_DATABUS_DIR,
|
|
|
+ input SNES_SYSCLK,
|
|
|
+
|
|
|
+ /* SRAM signals */
|
|
|
+ /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
|
|
|
+ inout [15:0] ROM_DATA,
|
|
|
+ output [22:0] ROM_ADDR,
|
|
|
+ output ROM_CE,
|
|
|
+ output ROM_OE,
|
|
|
+ output ROM_WE,
|
|
|
+ output ROM_BHE,
|
|
|
+ output ROM_BLE,
|
|
|
+
|
|
|
+ /* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
|
|
|
+ inout [7:0] RAM_DATA,
|
|
|
+ output [18:0] RAM_ADDR,
|
|
|
+ output RAM_CE,
|
|
|
+ output RAM_OE,
|
|
|
+ output RAM_WE,
|
|
|
+
|
|
|
+ /* MCU signals */
|
|
|
+ input SPI_MOSI,
|
|
|
+ inout SPI_MISO,
|
|
|
+ input SPI_SS,
|
|
|
+ inout SPI_SCK,
|
|
|
+ input MCU_OVR,
|
|
|
+ output MCU_RDY,
|
|
|
+
|
|
|
+ output DAC_MCLK,
|
|
|
+ output DAC_LRCK,
|
|
|
+ output DAC_SDOUT,
|
|
|
+
|
|
|
+ /* SD signals */
|
|
|
+ input [3:0] SD_DAT,
|
|
|
+ inout SD_CMD,
|
|
|
+ inout SD_CLK,
|
|
|
+
|
|
|
+ /* debug */
|
|
|
+ output p113_out
|
|
|
+);
|
|
|
+
|
|
|
assign DAC_MCLK = 1'b0;
|
|
|
assign DAC_LRCK = 1'b0;
|
|
|
assign DAC_SDOUT = 1'b0;
|
|
|
|
|
|
+assign SD_CMD = 1'bZ;
|
|
|
+assign SD_CLK = 1'bZ;
|
|
|
+
|
|
|
wire [7:0] spi_cmd_data;
|
|
|
wire [7:0] spi_param_data;
|
|
|
wire [7:0] spi_input_data;
|
|
@@ -79,441 +88,318 @@ wire [2:0] spi_bit_cnt;
|
|
|
wire [23:0] MCU_ADDR;
|
|
|
wire [7:0] mcu_data_in;
|
|
|
wire [7:0] mcu_data_out;
|
|
|
-wire [7:0] MCU_IN_DATA;
|
|
|
-wire [7:0] MCU_OUT_DATA;
|
|
|
wire [3:0] MAPPER;
|
|
|
wire [23:0] SAVERAM_MASK;
|
|
|
wire [23:0] ROM_MASK;
|
|
|
-wire [7:0] SD_DMA_SRAM_DATA;
|
|
|
-wire [1:0] SD_DMA_TGT;
|
|
|
-wire [10:0] SD_DMA_PARTIAL_START;
|
|
|
-wire [10:0] SD_DMA_PARTIAL_END;
|
|
|
-
|
|
|
-wire [10:0] dac_addr;
|
|
|
-//wire [7:0] dac_volume;
|
|
|
-wire [7:0] msu_volumerq_out;
|
|
|
-wire [6:0] msu_status_out;
|
|
|
-wire [31:0] msu_addressrq_out;
|
|
|
-wire [15:0] msu_trackrq_out;
|
|
|
-wire [13:0] msu_write_addr;
|
|
|
-wire [13:0] msu_ptr_addr;
|
|
|
-wire [7:0] MSU_SNES_DATA_IN;
|
|
|
-wire [7:0] MSU_SNES_DATA_OUT;
|
|
|
-wire [5:0] msu_status_reset_bits;
|
|
|
-wire [5:0] msu_status_set_bits;
|
|
|
-
|
|
|
-
|
|
|
-spi snes_spi(.clk(CLK2),
|
|
|
- .MOSI(SPI_MOSI),
|
|
|
- .MISO(SPI_MISO),
|
|
|
- .SSEL(SPI_SS),
|
|
|
- .SCK(SPI_SCK),
|
|
|
- .cmd_ready(spi_cmd_ready),
|
|
|
- .param_ready(spi_param_ready),
|
|
|
- .cmd_data(spi_cmd_data),
|
|
|
- .param_data(spi_param_data),
|
|
|
- .endmessage(spi_endmessage),
|
|
|
- .startmessage(spi_startmessage),
|
|
|
- .input_data(spi_input_data),
|
|
|
- .byte_cnt(spi_byte_cnt),
|
|
|
- .bit_cnt(spi_bit_cnt)
|
|
|
+
|
|
|
+wire [23:0] MAPPED_SNES_ADDR;
|
|
|
+wire ROM_ADDR0;
|
|
|
+
|
|
|
+spi snes_spi(
|
|
|
+ .clk(CLK2),
|
|
|
+ .MOSI(SPI_MOSI),
|
|
|
+ .MISO(SPI_MISO),
|
|
|
+ .SSEL(SPI_SS),
|
|
|
+ .SCK(SPI_SCK),
|
|
|
+ .cmd_ready(spi_cmd_ready),
|
|
|
+ .param_ready(spi_param_ready),
|
|
|
+ .cmd_data(spi_cmd_data),
|
|
|
+ .param_data(spi_param_data),
|
|
|
+ .endmessage(spi_endmessage),
|
|
|
+ .startmessage(spi_startmessage),
|
|
|
+ .input_data(spi_input_data),
|
|
|
+ .byte_cnt(spi_byte_cnt),
|
|
|
+ .bit_cnt(spi_bit_cnt)
|
|
|
);
|
|
|
|
|
|
+reg [7:0] MCU_DINr;
|
|
|
+wire [7:0] MCU_DOUT;
|
|
|
|
|
|
mcu_cmd snes_mcu_cmd(
|
|
|
- .clk(CLK2),
|
|
|
- .cmd_ready(spi_cmd_ready),
|
|
|
- .param_ready(spi_param_ready),
|
|
|
- .cmd_data(spi_cmd_data),
|
|
|
- .param_data(spi_param_data),
|
|
|
- .mcu_mapper(MAPPER),
|
|
|
- .mcu_sram_size(SRAM_SIZE),
|
|
|
- .mcu_read(MCU_READ),
|
|
|
- .mcu_write(MCU_WRITE),
|
|
|
- .mcu_data_in(MCU_OUT_DATA),
|
|
|
- .mcu_data_out(MCU_IN_DATA),
|
|
|
- .spi_byte_cnt(spi_byte_cnt),
|
|
|
- .spi_bit_cnt(spi_bit_cnt),
|
|
|
- .spi_data_out(spi_input_data),
|
|
|
- .addr_out(MCU_ADDR),
|
|
|
- .endmessage(spi_endmessage),
|
|
|
- .startmessage(spi_startmessage),
|
|
|
- .saveram_mask_out(SAVERAM_MASK),
|
|
|
- .rom_mask_out(ROM_MASK)
|
|
|
+ .clk(CLK2),
|
|
|
+ .cmd_ready(spi_cmd_ready),
|
|
|
+ .param_ready(spi_param_ready),
|
|
|
+ .cmd_data(spi_cmd_data),
|
|
|
+ .param_data(spi_param_data),
|
|
|
+ .mcu_sram_size(SRAM_SIZE),
|
|
|
+ .mcu_write(MCU_WRITE),
|
|
|
+ .mcu_data_in(MCU_DINr),
|
|
|
+ .mcu_data_out(MCU_DOUT),
|
|
|
+ .spi_byte_cnt(spi_byte_cnt),
|
|
|
+ .spi_bit_cnt(spi_bit_cnt),
|
|
|
+ .spi_data_out(spi_input_data),
|
|
|
+ .addr_out(MCU_ADDR),
|
|
|
+ .endmessage(spi_endmessage),
|
|
|
+ .startmessage(spi_startmessage),
|
|
|
+ .saveram_mask_out(SAVERAM_MASK),
|
|
|
+ .rom_mask_out(ROM_MASK),
|
|
|
+ .mcu_rrq(MCU_RRQ),
|
|
|
+ .mcu_wrq(MCU_WRQ),
|
|
|
+ .mcu_rq_rdy(MCU_RDY)
|
|
|
);
|
|
|
|
|
|
// dcm1: dfs 4x
|
|
|
-my_dcm snes_dcm(.CLKIN(CLKIN),
|
|
|
- .CLKFX(CLK2),
|
|
|
- .LOCKED(DCM_LOCKED),
|
|
|
- .RST(DCM_RST),
|
|
|
- .STATUS(DCM_STATUS)
|
|
|
- );
|
|
|
-
|
|
|
-assign DCM_RST=0;
|
|
|
+my_dcm snes_dcm(
|
|
|
+ .CLKIN(CLKIN),
|
|
|
+ .CLKFX(CLK2),
|
|
|
+ .LOCKED(DCM_LOCKED),
|
|
|
+ .RST(DCM_RST),
|
|
|
+ .STATUS(DCM_STATUS)
|
|
|
+);
|
|
|
|
|
|
-/*
|
|
|
-dcm_srl16 snes_dcm_resetter(.CLK(CLKIN),
|
|
|
- .Q(DCM_RST)
|
|
|
- );
|
|
|
-*/
|
|
|
-//wire DCM_FX_STOPPED = DCM_STATUS[2];
|
|
|
-//always @(posedge CLKIN) begin
|
|
|
-// if(DCM_FX_STOPPED)
|
|
|
-// DCM_RSTr <= 1'b1;
|
|
|
-// else
|
|
|
-// DCM_RSTr <= 1'b0;
|
|
|
-//end
|
|
|
-
|
|
|
-/*reg DO_DCM_RESET, DCM_RESETTING;
|
|
|
-reg DCM_RSTr;
|
|
|
-assign DCM_RST = DCM_RSTr;
|
|
|
-reg [2:0] DCM_RESET_CNT;
|
|
|
-initial DO_DCM_RESET = 1'b0;
|
|
|
-initial DCM_RESETTING = 1'b0;
|
|
|
-
|
|
|
-always @(posedge CLKIN) begin
|
|
|
- if(!DCM_LOCKED && !DCM_RESETTING) begin
|
|
|
- DCM_RSTr <= 1'b1;
|
|
|
- DO_DCM_RESET <= 1'b1;
|
|
|
- DCM_RESET_CNT <= 3'b0;
|
|
|
- end else if (DO_DCM_RESET) begin
|
|
|
- DCM_RSTr <= 1'b0;
|
|
|
- DCM_RESET_CNT <= DCM_RESET_CNT + 1;
|
|
|
- end
|
|
|
-end
|
|
|
+assign DCM_RST=0;
|
|
|
|
|
|
-always @(posedge CLKIN) begin
|
|
|
- if (DO_DCM_RESET)
|
|
|
- DCM_RESETTING <= 1'b1;
|
|
|
- else if (DCM_RESET_CNT == 3'b110)
|
|
|
- DCM_RESETTING <= 1'b0;
|
|
|
-end
|
|
|
-*/
|
|
|
-wire SNES_RW;
|
|
|
-reg [1:0] SNES_READr;
|
|
|
-reg [1:0] SNES_WRITEr;
|
|
|
-reg [1:0] SNES_CSr;
|
|
|
-reg [5:0] SNES_CPU_CLKr;
|
|
|
+reg [5:0] SNES_READr;
|
|
|
+reg [5:0] SNES_WRITEr;
|
|
|
+reg [12:0] SNES_CPU_CLKr;
|
|
|
reg [5:0] SNES_RWr;
|
|
|
reg [23:0] SNES_ADDRr;
|
|
|
-reg [23:0] SNES_ADDR_PREVr;
|
|
|
-reg [3:0] SNES_ADDRCHGr;
|
|
|
|
|
|
-wire SNES_READs = (SNES_READr == 2'b11);
|
|
|
-wire SNES_WRITEs = (SNES_WRITEr == 2'b11);
|
|
|
-wire SNES_CSs = (SNES_CSr == 2'b11);
|
|
|
-wire SNES_CPU_CLKs = SNES_CPU_CLK; // (SNES_CPU_CLKr == 2'b11);
|
|
|
-wire SNES_RW_start = (SNES_RWr == 6'b111110); // falling edge marks beginning of cycle
|
|
|
-wire SNES_cycle_start = (SNES_CPU_CLKr == 6'b000001);
|
|
|
-wire SNES_ADDRCHG = (SNES_ADDRr != SNES_ADDR_PREVr);
|
|
|
-wire SNES_addr_start = (SNES_ADDRCHGr[0] == 1'b1);
|
|
|
+wire SNES_RW = (SNES_READ & SNES_WRITE);
|
|
|
|
|
|
-assign SNES_RW = (SNES_READ & SNES_WRITE);
|
|
|
+wire SNES_RW_start = (SNES_RWr == 6'b111110); // falling edge marks beginning of cycle
|
|
|
+wire SNES_RD_start = (SNES_READr == 6'b111110);
|
|
|
+wire SNES_WR_start = (SNES_WRITEr == 6'b111110);
|
|
|
+wire SNES_cycle_start = (SNES_CPU_CLKr[5:0] == 6'b000001);
|
|
|
+wire SNES_cycle_end = (SNES_CPU_CLKr[5:0] == 6'b111110);
|
|
|
|
|
|
always @(posedge CLK2) begin
|
|
|
- SNES_READr <= {SNES_READr[0], SNES_READ};
|
|
|
- SNES_WRITEr <= {SNES_WRITEr[0], SNES_WRITE};
|
|
|
- SNES_CSr <= {SNES_CSr[0], SNES_CS};
|
|
|
- SNES_CPU_CLKr <= {SNES_CPU_CLKr[4:0], SNES_CPU_CLK};
|
|
|
- SNES_RWr <= {SNES_RWr[4:0], SNES_RW};
|
|
|
+ SNES_READr <= {SNES_READr[4:0], SNES_READ};
|
|
|
+ SNES_WRITEr <= {SNES_WRITEr[4:0], SNES_WRITE};
|
|
|
+ SNES_CPU_CLKr <= {SNES_CPU_CLKr[11:0], SNES_CPU_CLK};
|
|
|
+ SNES_RWr <= {SNES_RWr[4:0], SNES_RW};
|
|
|
end
|
|
|
|
|
|
-reg ADDR_WRITE;
|
|
|
-
|
|
|
-//reg [23:0] SNES_ADDRr;
|
|
|
-//wire [23:0] SNES_ADDRw = SNES_ADDR;
|
|
|
-
|
|
|
wire ROM_SEL;
|
|
|
|
|
|
address snes_addr(
|
|
|
- .CLK(CLK2),
|
|
|
- .MAPPER(MAPPER),
|
|
|
- .SNES_ADDR(SNES_ADDR), // requested address from SNES
|
|
|
- .SNES_CS(SNES_CS), // "CART" pin from SNES (active low)
|
|
|
- .ROM_ADDR(ROM_ADDR), // Address to request from SRAM (active low)
|
|
|
- .ROM_SEL(ROM_SEL), // which SRAM unit to access
|
|
|
- .MCU_OVR(MCU_OVR), // enable MCU mode (active low)
|
|
|
- .MODE(MODE), // MCU(1) or SNES(0) ("bus phase")
|
|
|
- .IS_SAVERAM(IS_SAVERAM),
|
|
|
- .IS_ROM(IS_ROM),
|
|
|
- .MCU_ADDR(MCU_ADDR),
|
|
|
- .ROM_ADDR0(ROM_ADDR0),
|
|
|
- .SAVERAM_MASK(SAVERAM_MASK),
|
|
|
- .ROM_MASK(ROM_MASK)
|
|
|
- );
|
|
|
+ .CLK(CLK2),
|
|
|
+ .SNES_ADDR(SNES_ADDR), // requested address from SNES
|
|
|
+ .SNES_CS(SNES_CS), // "CART" pin from SNES (active low)
|
|
|
+ .ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
|
|
|
+ .ROM_SEL(ROM_SEL), // which SRAM unit to access
|
|
|
+ .IS_SAVERAM(IS_SAVERAM),
|
|
|
+ .IS_ROM(IS_ROM),
|
|
|
+ .MCU_ADDR(MCU_ADDR),
|
|
|
+ .SAVERAM_MASK(SAVERAM_MASK),
|
|
|
+ .ROM_MASK(ROM_MASK)
|
|
|
+);
|
|
|
|
|
|
wire SNES_READ_CYCLEw;
|
|
|
wire SNES_WRITE_CYCLEw;
|
|
|
wire MCU_READ_CYCLEw;
|
|
|
wire MCU_WRITE_CYCLEw;
|
|
|
|
|
|
-data snes_data(.CLK(CLK2),
|
|
|
- .SNES_READ(SNES_READ),
|
|
|
- .SNES_WRITE(SNES_WRITE),
|
|
|
- .MCU_READ(MCU_READ),
|
|
|
- .MCU_WRITE(MCU_WRITE),
|
|
|
- .SNES_DATA(SNES_DATA),
|
|
|
- .ROM_DATA(ROM_DATA),
|
|
|
- .MODE(MODE),
|
|
|
- .SNES_DATA_TO_MEM(SNES_DATA_TO_MEM),
|
|
|
- .MCU_DATA_TO_MEM(MCU_DATA_TO_MEM),
|
|
|
- .ROM_DATA_TO_SNES_MEM(ROM_DATA_TO_SNES_MEM),
|
|
|
- .ROM_DATA_TO_MCU_MEM(ROM_DATA_TO_MCU_MEM),
|
|
|
- .MCU_OVR(MCU_OVR),
|
|
|
- .MCU_IN_DATA(MCU_IN_DATA),
|
|
|
- .MCU_OUT_DATA(MCU_OUT_DATA),
|
|
|
- .ROM_ADDR0(ROM_ADDR0),
|
|
|
- .MSU_DATA_IN(MSU_SNES_DATA_IN),
|
|
|
- .MSU_DATA_OUT(MSU_SNES_DATA_OUT),
|
|
|
- .msu_enable(msu_enable)
|
|
|
- );
|
|
|
-
|
|
|
parameter MODE_SNES = 1'b0;
|
|
|
parameter MODE_MCU = 1'b1;
|
|
|
|
|
|
-parameter STATE_0 = 14'b00000000000001;
|
|
|
-parameter STATE_1 = 14'b00000000000010;
|
|
|
-parameter STATE_2 = 14'b00000000000100;
|
|
|
-parameter STATE_3 = 14'b00000000001000;
|
|
|
-parameter STATE_4 = 14'b00000000010000;
|
|
|
-parameter STATE_5 = 14'b00000000100000;
|
|
|
-parameter STATE_6 = 14'b00000001000000;
|
|
|
-parameter STATE_7 = 14'b00000010000000;
|
|
|
-parameter STATE_8 = 14'b00000100000000;
|
|
|
-parameter STATE_9 = 14'b00001000000000;
|
|
|
-parameter STATE_10 = 14'b00010000000000;
|
|
|
-parameter STATE_11 = 14'b00100000000000;
|
|
|
-parameter STATE_12 = 14'b01000000000000;
|
|
|
-parameter STATE_IDLE = 14'b10000000000000;
|
|
|
-
|
|
|
-reg [13:0] STATE;
|
|
|
-reg [3:0] STATEIDX;
|
|
|
+parameter ST_IDLE = 18'b000000000000000001;
|
|
|
+parameter ST_SNES_RD_ADDR = 18'b000000000000000010;
|
|
|
+parameter ST_SNES_RD_WAIT = 18'b000000000000000100;
|
|
|
+parameter ST_SNES_RD_END = 18'b000000000000001000;
|
|
|
+parameter ST_SNES_WR_ADDR = 18'b000000000000010000;
|
|
|
+parameter ST_SNES_WR_WAIT1= 18'b000000000000100000;
|
|
|
+parameter ST_SNES_WR_DATA = 18'b000000000001000000;
|
|
|
+parameter ST_SNES_WR_WAIT2= 18'b000000000010000000;
|
|
|
+parameter ST_SNES_WR_END = 18'b000000000100000000;
|
|
|
+parameter ST_MCU_RD_ADDR = 18'b000000001000000000;
|
|
|
+parameter ST_MCU_RD_WAIT = 18'b000000010000000000;
|
|
|
+parameter ST_MCU_RD_WAIT2 = 18'b000000100000000000;
|
|
|
+parameter ST_MCU_RD_END = 18'b000001000000000000;
|
|
|
+parameter ST_MCU_WR_ADDR = 18'b000010000000000000;
|
|
|
+parameter ST_MCU_WR_WAIT = 18'b000100000000000000;
|
|
|
+parameter ST_MCU_WR_WAIT2 = 18'b001000000000000000;
|
|
|
+parameter ST_MCU_WR_END = 18'b010000000000000000;
|
|
|
+
|
|
|
+parameter ROM_RD_WAIT = 4'h4;
|
|
|
+parameter ROM_RD_WAIT_MCU = 4'h5;
|
|
|
+parameter ROM_WR_WAIT1 = 4'h2;
|
|
|
+parameter ROM_WR_WAIT2 = 4'h3;
|
|
|
+parameter ROM_WR_WAIT_MCU = 4'h6;
|
|
|
+
|
|
|
+reg [17:0] STATE;
|
|
|
+initial STATE = ST_IDLE;
|
|
|
|
|
|
reg [1:0] CYCLE_RESET;
|
|
|
reg ROM_WE_MASK;
|
|
|
reg ROM_OE_MASK;
|
|
|
|
|
|
-reg [13:0] ROM_WE_ARRAY [3:0];
|
|
|
-reg [13:0] ROM_OE_ARRAY [3:0];
|
|
|
-
|
|
|
-reg [13:0] SNES_DATA_TO_MEM_ARRAY[1:0];
|
|
|
-reg [13:0] MCU_DATA_TO_MEM_ARRAY[1:0];
|
|
|
-reg [13:0] ROM_DATA_TO_SNES_MEM_ARRAY[1:0];
|
|
|
-reg [13:0] ROM_DATA_TO_MCU_MEM_ARRAY[1:0];
|
|
|
-
|
|
|
-reg [13:0] MODE_ARRAY;
|
|
|
-
|
|
|
-reg SNES_READ_CYCLE;
|
|
|
-reg SNES_WRITE_CYCLE;
|
|
|
-reg MCU_READ_CYCLE;
|
|
|
-reg MCU_WRITE_CYCLE;
|
|
|
-reg MCU_SPI_WRITEONCE;
|
|
|
-reg MCU_SPI_READONCE;
|
|
|
-reg MCU_SPI_WRITE;
|
|
|
-reg MCU_SPI_READ;
|
|
|
-reg MCU_SPI_ADDR_INCREMENT;
|
|
|
-reg [7:0] MCU_DATA_IN;
|
|
|
-reg [3:0] MAPPER_BUF;
|
|
|
-
|
|
|
-reg SNES_DATABUS_OE_BUF;
|
|
|
-reg SNES_DATABUS_DIR_BUF;
|
|
|
-
|
|
|
-assign MODE = !MCU_OVR ? MODE_MCU : MODE_ARRAY[STATEIDX];
|
|
|
-
|
|
|
-initial begin
|
|
|
- CYCLE_RESET = 2'b0;
|
|
|
-
|
|
|
- STATE = STATE_IDLE;
|
|
|
- STATEIDX = 13;
|
|
|
- ROM_WE_MASK = 1'b1;
|
|
|
- ROM_OE_MASK = 1'b1;
|
|
|
- SNES_READ_CYCLE = 1'b1;
|
|
|
- SNES_WRITE_CYCLE = 1'b1;
|
|
|
- MCU_READ_CYCLE = 1'b1;
|
|
|
- MCU_WRITE_CYCLE = 1'b1;
|
|
|
- MODE_ARRAY = 14'b0_000000_1111111;
|
|
|
-
|
|
|
- ROM_WE_ARRAY[2'b00] = 14'b1_000000_0000000;
|
|
|
- ROM_WE_ARRAY[2'b01] = 14'b1_000000_1111111;
|
|
|
- ROM_WE_ARRAY[2'b10] = 14'b1_111111_0000000;
|
|
|
- ROM_WE_ARRAY[2'b11] = 14'b1_111111_1111111;
|
|
|
-
|
|
|
- ROM_OE_ARRAY[2'b00] = 14'b1_111111_1111111;
|
|
|
- ROM_OE_ARRAY[2'b01] = 14'b1_111111_0000000;
|
|
|
- ROM_OE_ARRAY[2'b10] = 14'b0_000000_1111111;
|
|
|
- ROM_OE_ARRAY[2'b11] = 14'b0_000000_0000000;
|
|
|
-
|
|
|
- SNES_DATA_TO_MEM_ARRAY[1'b0] = 14'b0_000100_0000000; // SNES write
|
|
|
- /* 13'b0001000000000 */
|
|
|
- SNES_DATA_TO_MEM_ARRAY[1'b1] = 14'b0_000000_0000000; // SNES read
|
|
|
-
|
|
|
- MCU_DATA_TO_MEM_ARRAY[1'b0] = 14'b1_111111_1111111; // MCU write
|
|
|
-// MCU_DATA_TO_MEM_ARRAY[1'b0] = 13'b0000000001000; // MCU write
|
|
|
-
|
|
|
- MCU_DATA_TO_MEM_ARRAY[1'b1] = 14'b0_000000_0000000; // MCU read
|
|
|
-
|
|
|
- ROM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 14'b0_000000_0000000; // SNES write
|
|
|
- ROM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 14'b0_000010_0000000; // SNES read
|
|
|
- /* 13'b0000100000000; */
|
|
|
-
|
|
|
- ROM_DATA_TO_MCU_MEM_ARRAY[1'b0] = 14'b0_000000_0000000; // MCU write
|
|
|
- ROM_DATA_TO_MCU_MEM_ARRAY[1'b1] = 14'b0_000000_0000001; // MCU read
|
|
|
-// SRAM_DATA_TO_MCU_MEM_ARRAY[1'b1] = 13'b0000000000001; // MCU read
|
|
|
-
|
|
|
-end
|
|
|
-
|
|
|
-// falling edge of SNES /RD or /WR marks the beginning of a new cycle
|
|
|
-// SNES READ or WRITE always starts @posedge CLK !!
|
|
|
-// CPU cycle can be 6, 8 or 12 CLKIN cycles so we must satisfy
|
|
|
-// the minimum of 6 SNES cycles to get everything done.
|
|
|
-// we have 24 internal cycles to work with. (CLKIN * 4)
|
|
|
+reg [7:0] SNES_DINr;
|
|
|
+reg [7:0] ROM_DOUTr;
|
|
|
+
|
|
|
+assign SNES_DATA = (!SNES_READ) ? SNES_DINr : 8'bZ;
|
|
|
|
|
|
+reg [3:0] ST_MEM_DELAYr;
|
|
|
+reg MCU_RD_PENDr;
|
|
|
+reg MCU_WR_PENDr;
|
|
|
+reg [23:0] ROM_ADDRr;
|
|
|
+reg NEED_SNES_ADDRr;
|
|
|
always @(posedge CLK2) begin
|
|
|
- CYCLE_RESET <= {CYCLE_RESET[0], SNES_cycle_start};
|
|
|
+ if(SNES_cycle_end) NEED_SNES_ADDRr <= 1'b1;
|
|
|
+ else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0;
|
|
|
end
|
|
|
|
|
|
+wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr;
|
|
|
+
|
|
|
+assign ROM_ADDR = (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
|
|
|
+assign ROM_ADDR0 = (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
|
|
|
+
|
|
|
+reg ROM_WEr;
|
|
|
+initial ROM_WEr = 1'b1;
|
|
|
+
|
|
|
+reg RQ_MCU_RDYr;
|
|
|
+initial RQ_MCU_RDYr = 1'b1;
|
|
|
+assign MCU_RDY = RQ_MCU_RDYr;
|
|
|
+
|
|
|
always @(posedge CLK2) begin
|
|
|
- MCU_READ_CYCLE <= MCU_READ;
|
|
|
- MCU_WRITE_CYCLE <= MCU_WRITE;
|
|
|
- if (SNES_cycle_start) begin
|
|
|
- SNES_READ_CYCLE <= SNES_READ;
|
|
|
- SNES_WRITE_CYCLE <= SNES_WRITE;
|
|
|
- STATE <= STATE_0;
|
|
|
- STATEIDX <= 12;
|
|
|
- end else begin
|
|
|
- case (STATE)
|
|
|
- STATE_0: begin
|
|
|
- STATE <= STATE_1; STATEIDX <= 11;
|
|
|
- end
|
|
|
- STATE_1: begin
|
|
|
- STATE <= STATE_2; STATEIDX <= 10;
|
|
|
- end
|
|
|
- STATE_2: begin
|
|
|
- STATE <= STATE_3; STATEIDX <= 9;
|
|
|
- end
|
|
|
- STATE_3: begin
|
|
|
- STATE <= STATE_4; STATEIDX <= 8;
|
|
|
- end
|
|
|
- STATE_4: begin
|
|
|
- STATE <= STATE_5; STATEIDX <= 7;
|
|
|
- end
|
|
|
- STATE_5: begin
|
|
|
- STATE <= STATE_6; STATEIDX <= 6;
|
|
|
- end
|
|
|
- STATE_6: begin
|
|
|
- STATE <= STATE_7; STATEIDX <= 5;
|
|
|
- end
|
|
|
- STATE_7: begin
|
|
|
- STATE <= STATE_8; STATEIDX <= 4;
|
|
|
- end
|
|
|
- STATE_8: begin
|
|
|
- STATE <= STATE_9; STATEIDX <= 3;
|
|
|
- end
|
|
|
- STATE_9: begin
|
|
|
- STATE <= STATE_10; STATEIDX <= 2;
|
|
|
- end
|
|
|
- STATE_10: begin
|
|
|
- STATE <= STATE_11; STATEIDX <= 1;
|
|
|
- end
|
|
|
- STATE_11: begin
|
|
|
- STATE <= STATE_12; STATEIDX <= 0;
|
|
|
- end
|
|
|
- STATE_12: begin
|
|
|
- STATE <= STATE_IDLE; STATEIDX <= 13;
|
|
|
- end
|
|
|
- STATE_IDLE: begin
|
|
|
- STATE <= STATE_IDLE; STATEIDX <= 13;
|
|
|
- end
|
|
|
- default: begin
|
|
|
- STATE <= STATE_IDLE; STATEIDX <= 13;
|
|
|
- end
|
|
|
- endcase
|
|
|
- end
|
|
|
+ if(MCU_RRQ) begin
|
|
|
+ MCU_RD_PENDr <= 1'b1;
|
|
|
+ RQ_MCU_RDYr <= 1'b0;
|
|
|
+ end else if(MCU_WRQ) begin
|
|
|
+ MCU_WR_PENDr <= 1'b1;
|
|
|
+ RQ_MCU_RDYr <= 1'b0;
|
|
|
+ end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
|
|
|
+ MCU_RD_PENDr <= 1'b0;
|
|
|
+ MCU_WR_PENDr <= 1'b0;
|
|
|
+ RQ_MCU_RDYr <= 1'b1;
|
|
|
+ end
|
|
|
end
|
|
|
-/*
|
|
|
-always @(posedge CLK2) begin
|
|
|
|
|
|
- case (STATE)
|
|
|
- STATE_9: begin
|
|
|
- STATEIDX <= 9;
|
|
|
- end
|
|
|
-
|
|
|
- STATE_0: begin
|
|
|
- STATEIDX <= 8;
|
|
|
- end
|
|
|
-
|
|
|
- STATE_1: begin
|
|
|
- STATEIDX <= 7;
|
|
|
- end
|
|
|
-
|
|
|
- STATE_2: begin
|
|
|
- STATEIDX <= 6;
|
|
|
- end
|
|
|
-
|
|
|
- STATE_3: begin
|
|
|
- STATEIDX <= 5;
|
|
|
- end
|
|
|
-
|
|
|
- STATE_4: begin
|
|
|
- STATEIDX <= 4;
|
|
|
- end
|
|
|
-
|
|
|
- STATE_5: begin
|
|
|
- STATEIDX <= 3;
|
|
|
- end
|
|
|
-
|
|
|
- STATE_6: begin
|
|
|
- STATEIDX <= 2;
|
|
|
- end
|
|
|
+reg snes_wr_cycle;
|
|
|
|
|
|
- STATE_7: begin
|
|
|
- STATEIDX <= 1;
|
|
|
+always @(posedge CLK2) begin
|
|
|
+ if(SNES_cycle_start) begin
|
|
|
+ STATE <= ST_SNES_RD_ADDR;
|
|
|
+ end else if(SNES_WR_start) begin
|
|
|
+ STATE <= ST_SNES_WR_ADDR;
|
|
|
+ end else begin
|
|
|
+ case(STATE)
|
|
|
+ ST_IDLE: begin
|
|
|
+ ROM_ADDRr <= MAPPED_SNES_ADDR;
|
|
|
+ if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
|
|
|
+ else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR;
|
|
|
+ else STATE <= ST_IDLE;
|
|
|
+ end
|
|
|
+ ST_SNES_RD_ADDR: begin
|
|
|
+ STATE <= ST_SNES_RD_WAIT;
|
|
|
+ ST_MEM_DELAYr <= ROM_RD_WAIT;
|
|
|
+ end
|
|
|
+ ST_SNES_RD_WAIT: begin
|
|
|
+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
|
|
|
+ if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END;
|
|
|
+ else STATE <= ST_SNES_RD_WAIT;
|
|
|
+ if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
|
|
|
+ else SNES_DINr <= ROM_DATA[15:8];
|
|
|
+ end
|
|
|
+ ST_SNES_RD_END: begin
|
|
|
+ STATE <= ST_IDLE;
|
|
|
+ if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
|
|
|
+ else SNES_DINr <= ROM_DATA[15:8];
|
|
|
+ end
|
|
|
+ ST_SNES_WR_ADDR: begin
|
|
|
+ ROM_WEr <= (!IS_SAVERAM);
|
|
|
+ snes_wr_cycle <= 1'b1;
|
|
|
+ STATE <= ST_SNES_WR_WAIT1;
|
|
|
+ ST_MEM_DELAYr <= ROM_WR_WAIT1;
|
|
|
+ end
|
|
|
+ ST_SNES_WR_WAIT1: begin
|
|
|
+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
|
|
|
+ if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA;
|
|
|
+ else STATE <= ST_SNES_WR_WAIT1;
|
|
|
+ end
|
|
|
+ ST_SNES_WR_DATA: begin
|
|
|
+ ROM_DOUTr <= SNES_DATA;
|
|
|
+ ST_MEM_DELAYr <= ROM_WR_WAIT2;
|
|
|
+ STATE <= ST_SNES_WR_WAIT2;
|
|
|
+ end
|
|
|
+ ST_SNES_WR_WAIT2: begin
|
|
|
+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
|
|
|
+ if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END;
|
|
|
+ else STATE <= ST_SNES_WR_WAIT2;
|
|
|
+ end
|
|
|
+ ST_SNES_WR_END: begin
|
|
|
+ STATE <= ST_IDLE;
|
|
|
+ ROM_WEr <= 1'b1;
|
|
|
+ snes_wr_cycle <= 1'b0;
|
|
|
+ end
|
|
|
+ ST_MCU_RD_ADDR: begin
|
|
|
+ ROM_ADDRr <= MCU_ADDR;
|
|
|
+ STATE <= ST_MCU_RD_WAIT;
|
|
|
+ ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
|
|
|
+ end
|
|
|
+ ST_MCU_RD_WAIT: begin
|
|
|
+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
|
|
|
+ if(ST_MEM_DELAYr == 4'h0) begin
|
|
|
+ STATE <= ST_MCU_RD_WAIT2;
|
|
|
+ ST_MEM_DELAYr <= 4'h2;
|
|
|
+ end
|
|
|
+ else STATE <= ST_MCU_RD_WAIT;
|
|
|
+ if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0];
|
|
|
+ else MCU_DINr <= ROM_DATA[15:8];
|
|
|
end
|
|
|
-
|
|
|
- STATE_8: begin
|
|
|
- STATEIDX <= 0;
|
|
|
+ ST_MCU_RD_WAIT2: begin
|
|
|
+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
|
|
|
+ if(ST_MEM_DELAYr == 4'h0) begin
|
|
|
+ STATE <= ST_MCU_RD_END;
|
|
|
+ end else STATE <= ST_MCU_RD_WAIT2;
|
|
|
+ end
|
|
|
+ ST_MCU_RD_END: begin
|
|
|
+ STATE <= ST_IDLE;
|
|
|
+ end
|
|
|
+ ST_MCU_WR_ADDR: begin
|
|
|
+ ROM_ADDRr <= MCU_ADDR;
|
|
|
+ STATE <= ST_MCU_WR_WAIT;
|
|
|
+ ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
|
|
|
+ ROM_DOUTr <= MCU_DOUT;
|
|
|
+ ROM_WEr <= 1'b0;
|
|
|
+ end
|
|
|
+ ST_MCU_WR_WAIT: begin
|
|
|
+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
|
|
|
+ if(ST_MEM_DELAYr == 4'h0) begin
|
|
|
+ ROM_WEr <= 1'b1;
|
|
|
+ STATE <= ST_MCU_WR_WAIT2;
|
|
|
+ ST_MEM_DELAYr <= 4'h2;
|
|
|
+ end
|
|
|
+ else STATE <= ST_MCU_WR_WAIT;
|
|
|
end
|
|
|
- default:
|
|
|
- STATEIDX <= 9;
|
|
|
- endcase
|
|
|
+ ST_MCU_WR_WAIT2: begin
|
|
|
+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
|
|
|
+ if(ST_MEM_DELAYr == 4'h0) begin
|
|
|
+ STATE <= ST_MCU_WR_END;
|
|
|
+ end else STATE <= ST_MCU_WR_WAIT2;
|
|
|
+ end
|
|
|
+ ST_MCU_WR_END: begin
|
|
|
+ STATE <= ST_IDLE;
|
|
|
+ end
|
|
|
+
|
|
|
+ endcase
|
|
|
+ end
|
|
|
end
|
|
|
-*/
|
|
|
-// When in MCU mode, enable SRAM_WE according to MCU programming
|
|
|
-// else enable SRAM_WE according to state&cycle
|
|
|
-assign ROM_WE = !MCU_OVR ? MCU_WRITE
|
|
|
- : ((!IS_SAVERAM & !MODE) | ROM_WE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX]);
|
|
|
|
|
|
-// When in MCU mode, enable SRAM_OE whenever not writing
|
|
|
-// else enable SRAM_OE according to state&cycle
|
|
|
-assign ROM_OE = !MCU_OVR ? MCU_READ
|
|
|
- : ROM_OE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX];
|
|
|
+assign ROM_DATA[7:0] = ROM_ADDR0
|
|
|
+ ?(!ROM_WE ? ROM_DOUTr : 8'bZ)
|
|
|
+ :8'bZ;
|
|
|
+
|
|
|
+assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
|
|
|
+ :(!ROM_WE ? ROM_DOUTr : 8'bZ);
|
|
|
+
|
|
|
+assign ROM_WE = ROM_WEr | (ASSERT_SNES_ADDR & ~snes_wr_cycle);
|
|
|
+assign ROM_OE = 1'b0;
|
|
|
|
|
|
-assign ROM_CE = 1'b0; // !MCU_OVR ? (MCU_READ & MCU_WRITE) : ROM_SEL;
|
|
|
+assign ROM_CE = 1'b0;
|
|
|
|
|
|
assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0;
|
|
|
assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
|
|
|
|
|
|
-//assign SRAM_BHE = SRAM_ADDR0;
|
|
|
-//assign SRAM_BLE = ~SRAM_ADDR0;
|
|
|
+assign SNES_DATABUS_OE = ((IS_ROM & SNES_CS)
|
|
|
+ |(!IS_ROM & !IS_SAVERAM)
|
|
|
+ |(SNES_READ & SNES_WRITE)
|
|
|
+ );
|
|
|
|
|
|
-// dumb version
|
|
|
-//assign SRAM_OE = !MCU_ENA ? MCU_READ : SNES_READs;
|
|
|
-//assign SRAM_WE = !MCU_ENA ? MCU_WRITE : 1'b1;
|
|
|
-
|
|
|
-//assign SNES_DATABUS_OE = (!IS_SAVERAM & SNES_CS) | (SNES_READ & SNES_WRITE);
|
|
|
-assign SNES_DATABUS_OE = msu_enable ? 1'b0 : ((IS_ROM & SNES_CS) | (!IS_ROM & !IS_SAVERAM) | (SNES_READ & SNES_WRITE));
|
|
|
assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
|
|
|
|
|
|
-assign SNES_DATA_TO_MEM = SNES_DATA_TO_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];
|
|
|
-assign MCU_DATA_TO_MEM = MCU_DATA_TO_MEM_ARRAY[MCU_WRITE_CYCLE][STATEIDX];
|
|
|
-
|
|
|
-assign ROM_DATA_TO_SNES_MEM = ROM_DATA_TO_SNES_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];
|
|
|
-assign ROM_DATA_TO_MCU_MEM = ROM_DATA_TO_MCU_MEM_ARRAY[MCU_WRITE_CYCLE][STATEIDX];
|
|
|
+assign SNES_IRQ = 1'b0;
|
|
|
|
|
|
-assign SNES_READ_CYCLEw = SNES_READ_CYCLE;
|
|
|
-assign SNES_WRITE_CYCLEw = SNES_WRITE_CYCLE;
|
|
|
-assign IRQ_DIR = 1'b0;
|
|
|
-assign SNES_IRQ = 1'bZ;
|
|
|
+assign p113_out = 1'b0;
|
|
|
|
|
|
endmodule
|