main.v 9.9 KB

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  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: main
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Master Control FSM
  13. //
  14. // Dependencies: address
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module main(
  22. /* input clock */
  23. input CLKIN,
  24. /* SNES signals */
  25. input [23:0] SNES_ADDR,
  26. input SNES_READ,
  27. input SNES_WRITE,
  28. input SNES_CS,
  29. inout [7:0] SNES_DATA,
  30. input SNES_CPU_CLK,
  31. input SNES_REFRESH,
  32. output SNES_IRQ,
  33. output SNES_DATABUS_OE,
  34. output SNES_DATABUS_DIR,
  35. input SNES_SYSCLK,
  36. /* SRAM signals */
  37. /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
  38. inout [15:0] ROM_DATA,
  39. output [22:0] ROM_ADDR,
  40. output ROM_CE,
  41. output ROM_OE,
  42. output ROM_WE,
  43. output ROM_BHE,
  44. output ROM_BLE,
  45. /* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
  46. inout [7:0] RAM_DATA,
  47. output [18:0] RAM_ADDR,
  48. output RAM_CE,
  49. output RAM_OE,
  50. output RAM_WE,
  51. /* MCU signals */
  52. input SPI_MOSI,
  53. inout SPI_MISO,
  54. input SPI_SS,
  55. inout SPI_SCK,
  56. input MCU_OVR,
  57. output MCU_RDY,
  58. output DAC_MCLK,
  59. output DAC_LRCK,
  60. output DAC_SDOUT,
  61. /* SD signals */
  62. input [3:0] SD_DAT,
  63. inout SD_CMD,
  64. inout SD_CLK,
  65. /* debug */
  66. output p113_out
  67. );
  68. assign DAC_MCLK = 1'b0;
  69. assign DAC_LRCK = 1'b0;
  70. assign DAC_SDOUT = 1'b0;
  71. assign SD_CMD = 1'bZ;
  72. assign SD_CLK = 1'bZ;
  73. wire [7:0] spi_cmd_data;
  74. wire [7:0] spi_param_data;
  75. wire [7:0] spi_input_data;
  76. wire [31:0] spi_byte_cnt;
  77. wire [2:0] spi_bit_cnt;
  78. wire [23:0] MCU_ADDR;
  79. wire [7:0] mcu_data_in;
  80. wire [7:0] mcu_data_out;
  81. wire [3:0] MAPPER;
  82. wire [23:0] SAVERAM_MASK;
  83. wire [23:0] ROM_MASK;
  84. wire [23:0] MAPPED_SNES_ADDR;
  85. wire ROM_ADDR0;
  86. spi snes_spi(
  87. .clk(CLK2),
  88. .MOSI(SPI_MOSI),
  89. .MISO(SPI_MISO),
  90. .SSEL(SPI_SS),
  91. .SCK(SPI_SCK),
  92. .cmd_ready(spi_cmd_ready),
  93. .param_ready(spi_param_ready),
  94. .cmd_data(spi_cmd_data),
  95. .param_data(spi_param_data),
  96. .endmessage(spi_endmessage),
  97. .startmessage(spi_startmessage),
  98. .input_data(spi_input_data),
  99. .byte_cnt(spi_byte_cnt),
  100. .bit_cnt(spi_bit_cnt)
  101. );
  102. reg [7:0] MCU_DINr;
  103. wire [7:0] MCU_DOUT;
  104. mcu_cmd snes_mcu_cmd(
  105. .clk(CLK2),
  106. .cmd_ready(spi_cmd_ready),
  107. .param_ready(spi_param_ready),
  108. .cmd_data(spi_cmd_data),
  109. .param_data(spi_param_data),
  110. .mcu_sram_size(SRAM_SIZE),
  111. .mcu_write(MCU_WRITE),
  112. .mcu_data_in(MCU_DINr),
  113. .mcu_data_out(MCU_DOUT),
  114. .spi_byte_cnt(spi_byte_cnt),
  115. .spi_bit_cnt(spi_bit_cnt),
  116. .spi_data_out(spi_input_data),
  117. .addr_out(MCU_ADDR),
  118. .endmessage(spi_endmessage),
  119. .startmessage(spi_startmessage),
  120. .saveram_mask_out(SAVERAM_MASK),
  121. .rom_mask_out(ROM_MASK),
  122. .mcu_rrq(MCU_RRQ),
  123. .mcu_wrq(MCU_WRQ),
  124. .mcu_rq_rdy(MCU_RDY)
  125. );
  126. // dcm1: dfs 4x
  127. my_dcm snes_dcm(
  128. .CLKIN(CLKIN),
  129. .CLKFX(CLK2),
  130. .LOCKED(DCM_LOCKED),
  131. .RST(DCM_RST),
  132. .STATUS(DCM_STATUS)
  133. );
  134. assign DCM_RST=0;
  135. reg [5:0] SNES_READr;
  136. reg [5:0] SNES_WRITEr;
  137. reg [12:0] SNES_CPU_CLKr;
  138. reg [5:0] SNES_RWr;
  139. reg [23:0] SNES_ADDRr;
  140. wire SNES_RW = (SNES_READ & SNES_WRITE);
  141. wire SNES_RW_start = (SNES_RWr == 6'b111110); // falling edge marks beginning of cycle
  142. wire SNES_RD_start = (SNES_READr == 6'b111110);
  143. wire SNES_WR_start = (SNES_WRITEr == 6'b111110);
  144. wire SNES_cycle_start = (SNES_CPU_CLKr[5:0] == 6'b000001);
  145. wire SNES_cycle_end = (SNES_CPU_CLKr[5:0] == 6'b111110);
  146. always @(posedge CLK2) begin
  147. SNES_READr <= {SNES_READr[4:0], SNES_READ};
  148. SNES_WRITEr <= {SNES_WRITEr[4:0], SNES_WRITE};
  149. SNES_CPU_CLKr <= {SNES_CPU_CLKr[11:0], SNES_CPU_CLK};
  150. SNES_RWr <= {SNES_RWr[4:0], SNES_RW};
  151. end
  152. wire ROM_SEL;
  153. address snes_addr(
  154. .CLK(CLK2),
  155. .SNES_ADDR(SNES_ADDR), // requested address from SNES
  156. .SNES_CS(SNES_CS), // "CART" pin from SNES (active low)
  157. .ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
  158. .ROM_SEL(ROM_SEL), // which SRAM unit to access
  159. .IS_SAVERAM(IS_SAVERAM),
  160. .IS_ROM(IS_ROM),
  161. .MCU_ADDR(MCU_ADDR),
  162. .SAVERAM_MASK(SAVERAM_MASK),
  163. .ROM_MASK(ROM_MASK)
  164. );
  165. wire SNES_READ_CYCLEw;
  166. wire SNES_WRITE_CYCLEw;
  167. wire MCU_READ_CYCLEw;
  168. wire MCU_WRITE_CYCLEw;
  169. parameter MODE_SNES = 1'b0;
  170. parameter MODE_MCU = 1'b1;
  171. parameter ST_IDLE = 18'b000000000000000001;
  172. parameter ST_SNES_RD_ADDR = 18'b000000000000000010;
  173. parameter ST_SNES_RD_WAIT = 18'b000000000000000100;
  174. parameter ST_SNES_RD_END = 18'b000000000000001000;
  175. parameter ST_SNES_WR_ADDR = 18'b000000000000010000;
  176. parameter ST_SNES_WR_WAIT1= 18'b000000000000100000;
  177. parameter ST_SNES_WR_DATA = 18'b000000000001000000;
  178. parameter ST_SNES_WR_WAIT2= 18'b000000000010000000;
  179. parameter ST_SNES_WR_END = 18'b000000000100000000;
  180. parameter ST_MCU_RD_ADDR = 18'b000000001000000000;
  181. parameter ST_MCU_RD_WAIT = 18'b000000010000000000;
  182. parameter ST_MCU_RD_WAIT2 = 18'b000000100000000000;
  183. parameter ST_MCU_RD_END = 18'b000001000000000000;
  184. parameter ST_MCU_WR_ADDR = 18'b000010000000000000;
  185. parameter ST_MCU_WR_WAIT = 18'b000100000000000000;
  186. parameter ST_MCU_WR_WAIT2 = 18'b001000000000000000;
  187. parameter ST_MCU_WR_END = 18'b010000000000000000;
  188. parameter ROM_RD_WAIT = 4'h4;
  189. parameter ROM_RD_WAIT_MCU = 4'h5;
  190. parameter ROM_WR_WAIT1 = 4'h2;
  191. parameter ROM_WR_WAIT2 = 4'h3;
  192. parameter ROM_WR_WAIT_MCU = 4'h6;
  193. reg [17:0] STATE;
  194. initial STATE = ST_IDLE;
  195. reg [1:0] CYCLE_RESET;
  196. reg ROM_WE_MASK;
  197. reg ROM_OE_MASK;
  198. reg [7:0] SNES_DINr;
  199. reg [7:0] ROM_DOUTr;
  200. assign SNES_DATA = (!SNES_READ) ? SNES_DINr : 8'bZ;
  201. reg [3:0] ST_MEM_DELAYr;
  202. reg MCU_RD_PENDr;
  203. reg MCU_WR_PENDr;
  204. reg [23:0] ROM_ADDRr;
  205. reg NEED_SNES_ADDRr;
  206. always @(posedge CLK2) begin
  207. if(SNES_cycle_end) NEED_SNES_ADDRr <= 1'b1;
  208. else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0;
  209. end
  210. wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr;
  211. assign ROM_ADDR = (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
  212. assign ROM_ADDR0 = (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
  213. reg ROM_WEr;
  214. initial ROM_WEr = 1'b1;
  215. reg RQ_MCU_RDYr;
  216. initial RQ_MCU_RDYr = 1'b1;
  217. assign MCU_RDY = RQ_MCU_RDYr;
  218. always @(posedge CLK2) begin
  219. if(MCU_RRQ) begin
  220. MCU_RD_PENDr <= 1'b1;
  221. RQ_MCU_RDYr <= 1'b0;
  222. end else if(MCU_WRQ) begin
  223. MCU_WR_PENDr <= 1'b1;
  224. RQ_MCU_RDYr <= 1'b0;
  225. end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
  226. MCU_RD_PENDr <= 1'b0;
  227. MCU_WR_PENDr <= 1'b0;
  228. RQ_MCU_RDYr <= 1'b1;
  229. end
  230. end
  231. reg snes_wr_cycle;
  232. always @(posedge CLK2) begin
  233. if(SNES_cycle_start) begin
  234. STATE <= ST_SNES_RD_ADDR;
  235. end else if(SNES_WR_start) begin
  236. STATE <= ST_SNES_WR_ADDR;
  237. end else begin
  238. case(STATE)
  239. ST_IDLE: begin
  240. ROM_ADDRr <= MAPPED_SNES_ADDR;
  241. if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
  242. else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR;
  243. else STATE <= ST_IDLE;
  244. end
  245. ST_SNES_RD_ADDR: begin
  246. STATE <= ST_SNES_RD_WAIT;
  247. ST_MEM_DELAYr <= ROM_RD_WAIT;
  248. end
  249. ST_SNES_RD_WAIT: begin
  250. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  251. if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END;
  252. else STATE <= ST_SNES_RD_WAIT;
  253. if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
  254. else SNES_DINr <= ROM_DATA[15:8];
  255. end
  256. ST_SNES_RD_END: begin
  257. STATE <= ST_IDLE;
  258. if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
  259. else SNES_DINr <= ROM_DATA[15:8];
  260. end
  261. ST_SNES_WR_ADDR: begin
  262. ROM_WEr <= (!IS_SAVERAM);
  263. snes_wr_cycle <= 1'b1;
  264. STATE <= ST_SNES_WR_WAIT1;
  265. ST_MEM_DELAYr <= ROM_WR_WAIT1;
  266. end
  267. ST_SNES_WR_WAIT1: begin
  268. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  269. if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA;
  270. else STATE <= ST_SNES_WR_WAIT1;
  271. end
  272. ST_SNES_WR_DATA: begin
  273. ROM_DOUTr <= SNES_DATA;
  274. ST_MEM_DELAYr <= ROM_WR_WAIT2;
  275. STATE <= ST_SNES_WR_WAIT2;
  276. end
  277. ST_SNES_WR_WAIT2: begin
  278. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  279. if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END;
  280. else STATE <= ST_SNES_WR_WAIT2;
  281. end
  282. ST_SNES_WR_END: begin
  283. STATE <= ST_IDLE;
  284. ROM_WEr <= 1'b1;
  285. snes_wr_cycle <= 1'b0;
  286. end
  287. ST_MCU_RD_ADDR: begin
  288. ROM_ADDRr <= MCU_ADDR;
  289. STATE <= ST_MCU_RD_WAIT;
  290. ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
  291. end
  292. ST_MCU_RD_WAIT: begin
  293. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  294. if(ST_MEM_DELAYr == 4'h0) begin
  295. STATE <= ST_MCU_RD_WAIT2;
  296. ST_MEM_DELAYr <= 4'h2;
  297. end
  298. else STATE <= ST_MCU_RD_WAIT;
  299. if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0];
  300. else MCU_DINr <= ROM_DATA[15:8];
  301. end
  302. ST_MCU_RD_WAIT2: begin
  303. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  304. if(ST_MEM_DELAYr == 4'h0) begin
  305. STATE <= ST_MCU_RD_END;
  306. end else STATE <= ST_MCU_RD_WAIT2;
  307. end
  308. ST_MCU_RD_END: begin
  309. STATE <= ST_IDLE;
  310. end
  311. ST_MCU_WR_ADDR: begin
  312. ROM_ADDRr <= MCU_ADDR;
  313. STATE <= ST_MCU_WR_WAIT;
  314. ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
  315. ROM_DOUTr <= MCU_DOUT;
  316. ROM_WEr <= 1'b0;
  317. end
  318. ST_MCU_WR_WAIT: begin
  319. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  320. if(ST_MEM_DELAYr == 4'h0) begin
  321. ROM_WEr <= 1'b1;
  322. STATE <= ST_MCU_WR_WAIT2;
  323. ST_MEM_DELAYr <= 4'h2;
  324. end
  325. else STATE <= ST_MCU_WR_WAIT;
  326. end
  327. ST_MCU_WR_WAIT2: begin
  328. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  329. if(ST_MEM_DELAYr == 4'h0) begin
  330. STATE <= ST_MCU_WR_END;
  331. end else STATE <= ST_MCU_WR_WAIT2;
  332. end
  333. ST_MCU_WR_END: begin
  334. STATE <= ST_IDLE;
  335. end
  336. endcase
  337. end
  338. end
  339. assign ROM_DATA[7:0] = ROM_ADDR0
  340. ?(!ROM_WE ? ROM_DOUTr : 8'bZ)
  341. :8'bZ;
  342. assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
  343. :(!ROM_WE ? ROM_DOUTr : 8'bZ);
  344. assign ROM_WE = ROM_WEr | (ASSERT_SNES_ADDR & ~snes_wr_cycle);
  345. assign ROM_OE = 1'b0;
  346. assign ROM_CE = 1'b0;
  347. assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0;
  348. assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
  349. assign SNES_DATABUS_OE = ((IS_ROM & SNES_CS)
  350. |(!IS_ROM & !IS_SAVERAM)
  351. |(SNES_READ & SNES_WRITE)
  352. );
  353. assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
  354. assign SNES_IRQ = 1'b0;
  355. assign p113_out = 1'b0;
  356. endmodule