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@@ -21,6 +21,7 @@
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module my_dcm (
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input CLKIN,
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output CLKFX,
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+ output CLK2X,
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output LOCKED,
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input CLKFB,
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input RST,
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@@ -37,18 +38,18 @@ module my_dcm (
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.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
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// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
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.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
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- .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
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+ .CLKFX_MULTIPLY(7), // Can be any integer from 2 to 32
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.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
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.CLKIN_PERIOD(47.000), // Specify period of input clock
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.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
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.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
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- .DESKEW_ADJUST("SOURCE_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
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+ .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
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// an integer from 0 to 15
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.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
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.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
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.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
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- .FACTORY_JF(16'hC080), // FACTORY JF values
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-// .LOC("DCM_X0Y0"),
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+ .FACTORY_JF(16'hFFFF), // FACTORY JF values
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+// .LOC("X0Y0"),
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.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
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.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
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) DCM_inst (
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