main.v 13 KB

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  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: main
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Master Control FSM
  13. //
  14. // Dependencies: address
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module main(
  22. /* input clock */
  23. input CLKIN,
  24. /* SNES signals */
  25. input [23:0] SNES_ADDR,
  26. input SNES_READ,
  27. input SNES_WRITE,
  28. input SNES_CS,
  29. inout [7:0] SNES_DATA,
  30. input SNES_CPU_CLK,
  31. input SNES_REFRESH,
  32. inout SNES_IRQ,
  33. output SNES_DATABUS_OE,
  34. output SNES_DATABUS_DIR,
  35. output IRQ_DIR,
  36. /* SRAM signals */
  37. inout [15:0] SRAM_DATA,
  38. output [19:0] SRAM_ADDR,
  39. output [3:0] SRAM_CE2,
  40. output SRAM_OE,
  41. output SRAM_WE,
  42. output SRAM_BHE,
  43. output SRAM_BLE,
  44. /* AVR signals */
  45. input SPI_MOSI,
  46. output SPI_MISO,
  47. input SPI_SS,
  48. input SPI_SCK,
  49. input AVR_ENA
  50. /* debug */
  51. //output DCM_IN_STOPPED,
  52. //output DCM_FX_STOPPED
  53. //input DCM_RST
  54. );
  55. wire [7:0] spi_cmd_data;
  56. wire [7:0] spi_param_data;
  57. wire [7:0] spi_input_data;
  58. wire [31:0] spi_byte_cnt;
  59. wire [2:0] spi_bit_cnt;
  60. wire [23:0] AVR_ADDR;
  61. wire [7:0] avr_data_in;
  62. wire [7:0] avr_data_out;
  63. wire [7:0] AVR_IN_DATA;
  64. wire [7:0] AVR_OUT_DATA;
  65. wire [3:0] MAPPER;
  66. wire [23:0] SAVERAM_MASK;
  67. wire [23:0] ROM_MASK;
  68. spi snes_spi(.clk(CLK2),
  69. .MOSI(SPI_MOSI),
  70. .MISO(SPI_MISO),
  71. .SSEL(SPI_SS),
  72. .SCK(SPI_SCK),
  73. .LED(SPI_LSB),
  74. .cmd_ready(spi_cmd_ready),
  75. .param_ready(spi_param_ready),
  76. .cmd_data(spi_cmd_data),
  77. .param_data(spi_param_data),
  78. .endmessage(spi_endmessage),
  79. .startmessage(spi_startmessage),
  80. .input_data(spi_input_data),
  81. .byte_cnt(spi_byte_cnt),
  82. .bit_cnt(spi_bit_cnt)
  83. );
  84. avr_cmd snes_avr_cmd(
  85. .clk(CLK2),
  86. .cmd_ready(spi_cmd_ready),
  87. .param_ready(spi_param_ready),
  88. .cmd_data(spi_cmd_data),
  89. .param_data(spi_param_data),
  90. .avr_mapper(MAPPER),
  91. .avr_sram_size(SRAM_SIZE),
  92. .avr_read(AVR_READ),
  93. .avr_write(AVR_WRITE),
  94. .avr_data_in(AVR_OUT_DATA),
  95. .avr_data_out(AVR_IN_DATA),
  96. .spi_byte_cnt(spi_byte_cnt),
  97. .spi_bit_cnt(spi_bit_cnt),
  98. .spi_data_out(spi_input_data),
  99. .addr_out(AVR_ADDR),
  100. .endmessage(spi_endmessage),
  101. .startmessage(spi_startmessage),
  102. .saveram_mask_out(SAVERAM_MASK),
  103. .rom_mask_out(ROM_MASK)
  104. );
  105. //wire [7:0] DCM_STATUS;
  106. // dcm1: dfs 4x
  107. my_dcm snes_dcm(.CLKIN(CLKIN),
  108. .CLKFX(CLK2),
  109. .LOCKED(DCM_LOCKED),
  110. .RST(DCM_RST),
  111. .STATUS(DCM_STATUS),
  112. .CLKFB(CLKFB),
  113. .CLK0(CLK0)
  114. );
  115. dcm_srl16 snes_dcm_resetter(.CLK(CLKIN),
  116. .Q(DCM_RST)
  117. );
  118. assign CLKFB = CLK0;
  119. //wire DCM_FX_STOPPED = DCM_STATUS[2];
  120. //always @(posedge CLKIN) begin
  121. // if(DCM_FX_STOPPED)
  122. // DCM_RSTr <= 1'b1;
  123. // else
  124. // DCM_RSTr <= 1'b0;
  125. //end
  126. /*reg DO_DCM_RESET, DCM_RESETTING;
  127. reg DCM_RSTr;
  128. assign DCM_RST = DCM_RSTr;
  129. reg [2:0] DCM_RESET_CNT;
  130. initial DO_DCM_RESET = 1'b0;
  131. initial DCM_RESETTING = 1'b0;
  132. always @(posedge CLKIN) begin
  133. if(!DCM_LOCKED && !DCM_RESETTING) begin
  134. DCM_RSTr <= 1'b1;
  135. DO_DCM_RESET <= 1'b1;
  136. DCM_RESET_CNT <= 3'b0;
  137. end else if (DO_DCM_RESET) begin
  138. DCM_RSTr <= 1'b0;
  139. DCM_RESET_CNT <= DCM_RESET_CNT + 1;
  140. end
  141. end
  142. always @(posedge CLKIN) begin
  143. if (DO_DCM_RESET)
  144. DCM_RESETTING <= 1'b1;
  145. else if (DCM_RESET_CNT == 3'b110)
  146. DCM_RESETTING <= 1'b0;
  147. end
  148. */
  149. wire SNES_RW;
  150. reg [1:0] SNES_READr;
  151. reg [1:0] SNES_WRITEr;
  152. reg [1:0] SNES_CSr;
  153. reg [5:0] SNES_CPU_CLKr;
  154. reg [5:0] SNES_RWr;
  155. reg [23:0] SNES_ADDRr;
  156. reg [23:0] SNES_ADDR_PREVr;
  157. reg [3:0] SNES_ADDRCHGr;
  158. wire SNES_READs = (SNES_READr == 2'b11);
  159. wire SNES_WRITEs = (SNES_WRITEr == 2'b11);
  160. wire SNES_CSs = (SNES_CSr == 2'b11);
  161. wire SNES_CPU_CLKs = SNES_CPU_CLK; // (SNES_CPU_CLKr == 2'b11);
  162. wire SNES_RW_start = (SNES_RWr == 6'b111110); // falling edge marks beginning of cycle
  163. wire SNES_cycle_start = (SNES_CPU_CLKr == 6'b000001);
  164. wire SNES_ADDRCHG = (SNES_ADDRr != SNES_ADDR_PREVr);
  165. wire SNES_addr_start = (SNES_ADDRCHGr[0] == 1'b1);
  166. assign SNES_RW = (SNES_READ & SNES_WRITE);
  167. always @(posedge CLK2) begin
  168. SNES_READr <= {SNES_READr[0], SNES_READ};
  169. SNES_WRITEr <= {SNES_WRITEr[0], SNES_WRITE};
  170. SNES_CSr <= {SNES_CSr[0], SNES_CS};
  171. SNES_CPU_CLKr <= {SNES_CPU_CLKr[4:0], SNES_CPU_CLK};
  172. SNES_RWr <= {SNES_RWr[4:0], SNES_RW};
  173. end
  174. reg ADDR_WRITE;
  175. //reg [23:0] SNES_ADDRr;
  176. //wire [23:0] SNES_ADDRw = SNES_ADDR;
  177. address snes_addr(
  178. .CLK(CLK2),
  179. .MAPPER(MAPPER),
  180. .SNES_ADDR(SNES_ADDR), // requested address from SNES
  181. .SNES_CS(SNES_CS), // "CART" pin from SNES (active low)
  182. .SRAM_ADDR(SRAM_ADDR), // Address to request from SRAM (active low)
  183. .ROM_SEL(SRAM_CE2), // which SRAM unit to access
  184. .AVR_ENA(AVR_ENA), // enable AVR mode (active low)
  185. .MODE(MODE), // AVR(1) or SNES(0) ("bus phase")
  186. .IS_SAVERAM(IS_SAVERAM),
  187. .IS_ROM(IS_ROM),
  188. .AVR_ADDR(AVR_ADDR),
  189. .SRAM_ADDR0(SRAM_ADDR0),
  190. .SAVERAM_MASK(SAVERAM_MASK),
  191. .ROM_MASK(ROM_MASK)
  192. );
  193. wire SNES_READ_CYCLEw;
  194. wire SNES_WRITE_CYCLEw;
  195. wire AVR_READ_CYCLEw;
  196. wire AVR_WRITE_CYCLEw;
  197. data snes_data(.CLK(CLK2),
  198. .SNES_READ(SNES_READ),
  199. .SNES_WRITE(SNES_WRITE),
  200. .AVR_READ(AVR_READ),
  201. .AVR_WRITE(AVR_WRITE),
  202. .SNES_DATA(SNES_DATA),
  203. .SRAM_DATA(SRAM_DATA),
  204. .MODE(MODE),
  205. .SNES_DATA_TO_MEM(SNES_DATA_TO_MEM),
  206. .AVR_DATA_TO_MEM(AVR_DATA_TO_MEM),
  207. .SRAM_DATA_TO_SNES_MEM(SRAM_DATA_TO_SNES_MEM),
  208. .SRAM_DATA_TO_AVR_MEM(SRAM_DATA_TO_AVR_MEM),
  209. .AVR_ENA(AVR_ENA),
  210. .AVR_IN_DATA(AVR_IN_DATA),
  211. .AVR_OUT_DATA(AVR_OUT_DATA),
  212. .SRAM_ADDR0(SRAM_ADDR0)
  213. );
  214. parameter MODE_SNES = 1'b0;
  215. parameter MODE_AVR = 1'b1;
  216. parameter STATE_0 = 13'b0000000000001;
  217. parameter STATE_1 = 13'b0000000000010;
  218. parameter STATE_2 = 13'b0000000000100;
  219. parameter STATE_3 = 13'b0000000001000;
  220. parameter STATE_4 = 13'b0000000010000;
  221. parameter STATE_5 = 13'b0000000100000;
  222. parameter STATE_6 = 13'b0000001000000;
  223. parameter STATE_7 = 13'b0000010000000;
  224. parameter STATE_8 = 13'b0000100000000;
  225. parameter STATE_9 = 13'b0001000000000;
  226. parameter STATE_10 = 13'b0010000000000;
  227. parameter STATE_11 = 13'b0100000000000;
  228. parameter STATE_IDLE = 13'b1000000000000;
  229. reg [12:0] STATE;
  230. reg [3:0] STATEIDX;
  231. reg [1:0] CYCLE_RESET;
  232. reg SRAM_WE_MASK;
  233. reg SRAM_OE_MASK;
  234. reg [12:0] SRAM_WE_ARRAY [3:0];
  235. reg [12:0] SRAM_OE_ARRAY [3:0];
  236. reg [12:0] SNES_DATA_TO_MEM_ARRAY[1:0];
  237. reg [12:0] AVR_DATA_TO_MEM_ARRAY[1:0];
  238. reg [12:0] SRAM_DATA_TO_SNES_MEM_ARRAY[1:0];
  239. reg [12:0] SRAM_DATA_TO_AVR_MEM_ARRAY[1:0];
  240. reg [12:0] MODE_ARRAY;
  241. reg SNES_READ_CYCLE;
  242. reg SNES_WRITE_CYCLE;
  243. reg AVR_READ_CYCLE;
  244. reg AVR_WRITE_CYCLE;
  245. reg AVR_SPI_WRITEONCE;
  246. reg AVR_SPI_READONCE;
  247. reg AVR_SPI_WRITE;
  248. reg AVR_SPI_READ;
  249. reg AVR_SPI_ADDR_INCREMENT;
  250. reg [7:0] AVR_DATA_IN;
  251. reg [3:0] MAPPER_BUF;
  252. reg SNES_DATABUS_OE_BUF;
  253. reg SNES_DATABUS_DIR_BUF;
  254. assign MODE = !AVR_ENA ? MODE_AVR : MODE_ARRAY[STATEIDX];
  255. initial begin
  256. CYCLE_RESET = 2'b0;
  257. STATE = STATE_IDLE;
  258. STATEIDX = 12;
  259. SRAM_WE_MASK = 1'b1;
  260. SRAM_OE_MASK = 1'b1;
  261. SNES_READ_CYCLE = 1'b1;
  262. SNES_WRITE_CYCLE = 1'b1;
  263. AVR_READ_CYCLE = 1'b1;
  264. AVR_WRITE_CYCLE = 1'b1;
  265. MODE_ARRAY = 13'b0000000111111;
  266. SRAM_WE_ARRAY[2'b00] = 13'b1000000000000;
  267. SRAM_WE_ARRAY[2'b01] = 13'b1000000111111;
  268. SRAM_WE_ARRAY[2'b10] = 13'b1111111000000;
  269. SRAM_WE_ARRAY[2'b11] = 13'b1111111111111;
  270. SRAM_OE_ARRAY[2'b00] = 13'b1111111111111;
  271. SRAM_OE_ARRAY[2'b01] = 13'b1111111000000;
  272. SRAM_OE_ARRAY[2'b10] = 13'b0000000111111;
  273. SRAM_OE_ARRAY[2'b11] = 13'b0000000000000;
  274. SNES_DATA_TO_MEM_ARRAY[1'b0] = 13'b0001000000000; // SNES write
  275. SNES_DATA_TO_MEM_ARRAY[1'b1] = 13'b0000000000000; // SNES read
  276. AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b0000000010000; // AVR write
  277. AVR_DATA_TO_MEM_ARRAY[1'b1] = 13'b0000000000000; // AVR read
  278. SRAM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 13'b0000000000000; // SNES write
  279. SRAM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 13'b0000100000000; // SNES read
  280. SRAM_DATA_TO_AVR_MEM_ARRAY[1'b0] = 13'b0000000000000; // AVR write
  281. SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 13'b0000000000001; // AVR read
  282. end
  283. // falling edge of SNES /RD or /WR marks the beginning of a new cycle
  284. // SNES READ or WRITE always starts @posedge CLK !!
  285. // CPU cycle can be 6, 8 or 12 CLKIN cycles so we must satisfy
  286. // the minimum of 6 SNES cycles to get everything done.
  287. // we have 24 internal cycles to work with. (CLKIN * 4)
  288. always @(posedge CLK2) begin
  289. CYCLE_RESET <= {CYCLE_RESET[0], SNES_cycle_start};
  290. end
  291. always @(posedge CLK2) begin
  292. if (SNES_RW_start) begin
  293. SNES_READ_CYCLE <= SNES_READ;
  294. SNES_WRITE_CYCLE <= SNES_WRITE;
  295. AVR_READ_CYCLE <= AVR_READ;
  296. AVR_WRITE_CYCLE <= AVR_WRITE;
  297. STATE <= STATE_0;
  298. STATEIDX <= 11;
  299. end else begin
  300. case (STATE)
  301. STATE_0: begin
  302. STATE <= STATE_1; STATEIDX <= 10;
  303. end
  304. STATE_1: begin
  305. STATE <= STATE_2; STATEIDX <= 9;
  306. end
  307. STATE_2: begin
  308. STATE <= STATE_3; STATEIDX <= 8;
  309. end
  310. STATE_3: begin
  311. STATE <= STATE_4; STATEIDX <= 7;
  312. end
  313. STATE_4: begin
  314. STATE <= STATE_5; STATEIDX <= 6;
  315. end
  316. STATE_5: begin
  317. STATE <= STATE_6; STATEIDX <= 5;
  318. end
  319. STATE_6: begin
  320. STATE <= STATE_7; STATEIDX <= 4;
  321. end
  322. STATE_7: begin
  323. STATE <= STATE_8; STATEIDX <= 3;
  324. end
  325. STATE_8: begin
  326. STATE <= STATE_9; STATEIDX <= 2;
  327. end
  328. STATE_9: begin
  329. STATE <= STATE_10; STATEIDX <= 1;
  330. end
  331. STATE_10: begin
  332. STATE <= STATE_11; STATEIDX <= 0;
  333. end
  334. STATE_11: begin
  335. STATE <= STATE_IDLE; STATEIDX <= 12;
  336. end
  337. STATE_IDLE: begin
  338. STATE <= STATE_IDLE; STATEIDX <= 12;
  339. end
  340. default: begin
  341. STATE <= STATE_IDLE; STATEIDX <= 12;
  342. end
  343. endcase
  344. end
  345. end
  346. /*
  347. always @(posedge CLK2) begin
  348. case (STATE)
  349. STATE_9: begin
  350. STATEIDX <= 9;
  351. end
  352. STATE_0: begin
  353. STATEIDX <= 8;
  354. end
  355. STATE_1: begin
  356. STATEIDX <= 7;
  357. end
  358. STATE_2: begin
  359. STATEIDX <= 6;
  360. end
  361. STATE_3: begin
  362. STATEIDX <= 5;
  363. end
  364. STATE_4: begin
  365. STATEIDX <= 4;
  366. end
  367. STATE_5: begin
  368. STATEIDX <= 3;
  369. end
  370. STATE_6: begin
  371. STATEIDX <= 2;
  372. end
  373. STATE_7: begin
  374. STATEIDX <= 1;
  375. end
  376. STATE_8: begin
  377. STATEIDX <= 0;
  378. end
  379. default:
  380. STATEIDX <= 9;
  381. endcase
  382. end
  383. */
  384. // When in AVR mode, enable SRAM_WE according to AVR programming
  385. // else enable SRAM_WE according to state&cycle
  386. assign SRAM_WE = !AVR_ENA ? AVR_WRITE
  387. : ((!IS_SAVERAM & !MODE) | SRAM_WE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX]);
  388. // When in AVR mode, enable SRAM_OE whenever not writing
  389. // else enable SRAM_OE according to state&cycle
  390. assign SRAM_OE = !AVR_ENA ? AVR_READ
  391. : SRAM_OE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX];
  392. assign SRAM_BHE = !SRAM_WE ? SRAM_ADDR0 : 1'b0;
  393. assign SRAM_BLE = !SRAM_WE ? !SRAM_ADDR0 : 1'b0;
  394. // dumb version
  395. //assign SRAM_OE = !AVR_ENA ? AVR_READ : SNES_READs;
  396. //assign SRAM_WE = !AVR_ENA ? AVR_WRITE : 1'b1;
  397. //assign SNES_DATABUS_OE = (!IS_SAVERAM & SNES_CS) | (SNES_READ & SNES_WRITE);
  398. assign SNES_DATABUS_OE = (IS_ROM & SNES_CS) | (!IS_ROM & !IS_SAVERAM) | (SNES_READ & SNES_WRITE);
  399. assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
  400. assign SNES_DATA_TO_MEM = SNES_DATA_TO_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];
  401. assign AVR_DATA_TO_MEM = AVR_DATA_TO_MEM_ARRAY[AVR_WRITE_CYCLE][STATEIDX];
  402. assign SRAM_DATA_TO_SNES_MEM = SRAM_DATA_TO_SNES_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];
  403. assign SRAM_DATA_TO_AVR_MEM = SRAM_DATA_TO_AVR_MEM_ARRAY[AVR_WRITE_CYCLE][STATEIDX];
  404. assign SNES_READ_CYCLEw = SNES_READ_CYCLE;
  405. assign SNES_WRITE_CYCLEw = SNES_WRITE_CYCLE;
  406. assign IRQ_DIR = 1'b0;
  407. assign SNES_IRQ = 1'bZ;
  408. endmodule