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@@ -71,27 +71,37 @@ parameter SRTC_COMMAND = 5'b00100;
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parameter SRTC_WRITE = 5'b01000;
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parameter SRTC_WRITE2 = 5'b10000;
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+reg [3:0] data_in_r;
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+
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+reg [3:0] addr_in_r;
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+always @(posedge clkin) addr_in_r <= {addr_in_r[2:0], addr_in};
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+
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+assign srtc_reg_we_rising = reg_we_rising;
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+assign srtc_state = mode_r;
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+assign srtc_rtc_ptr = rtc_ptr;
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+assign srtc_we_sreg = reg_we_sreg;
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+
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initial begin
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rtc_we_r = 0;
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- mode_r <= SRTC_READ;
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- rtc_ptr <= 4'hf;
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+ mode_r = SRTC_READ;
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+ rtc_ptr = 4'hf;
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+ data_out_r = 8'h00;
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+end
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+
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+//always @(posedge clkin) data_in_r <= data_in;
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+always @(posedge clkin) begin
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+ if(~reg_we) data_in_r <= data_in;
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end
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always @(posedge clkin) begin
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if(reset_rising) begin
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mode_r <= SRTC_READ;
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rtc_ptr <= 4'hf;
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- end else if(mode_r == SRTC_WRITE2) begin
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- we_countdown_r <= we_countdown_r - 1;
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- if (we_countdown_r == 3'b000) begin
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- mode_r <= SRTC_WRITE;
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- rtc_we_r <= 0;
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- end
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end else if(reg_we_rising && enable) begin
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- case (addr_in)
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+ case (addr_in_r[0])
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// 1'b0: // data register is read only
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1'b1: // control register
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- case (data_in)
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+ case (data_in_r)
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4'hd: begin
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mode_r <= SRTC_READ;
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rtc_ptr <= 4'hf;
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@@ -99,11 +109,9 @@ always @(posedge clkin) begin
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4'he: begin
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mode_r <= SRTC_COMMAND;
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end
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- 4'hf: begin
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- end
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default: begin
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if(mode_r == SRTC_COMMAND) begin
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- case (data_in)
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+ case (data_in_r)
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4'h0: begin
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mode_r <= SRTC_WRITE;
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rtc_data_out_r <= rtc_data_in;
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@@ -119,38 +127,38 @@ always @(posedge clkin) begin
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end else if(mode_r == SRTC_WRITE) begin
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rtc_ptr <= rtc_ptr + 1;
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case(rtc_ptr)
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- 0: rtc_data_out_r[3:0] <= data_in;
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- 1: rtc_data_out_r[7:4] <= data_in;
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- 2: rtc_data_out_r[11:8] <= data_in;
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- 3: rtc_data_out_r[15:12] <= data_in;
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- 4: rtc_data_out_r[19:16] <= data_in;
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- 5: rtc_data_out_r[23:20] <= data_in;
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- 6: rtc_data_out_r[27:24] <= data_in;
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- 7: rtc_data_out_r[31:28] <= data_in;
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+ 0: rtc_data_out_r[3:0] <= data_in_r;
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+ 1: rtc_data_out_r[7:4] <= data_in_r;
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+ 2: rtc_data_out_r[11:8] <= data_in_r;
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+ 3: rtc_data_out_r[15:12] <= data_in_r;
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+ 4: rtc_data_out_r[19:16] <= data_in_r;
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+ 5: rtc_data_out_r[23:20] <= data_in_r;
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+ 6: rtc_data_out_r[27:24] <= data_in_r;
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+ 7: rtc_data_out_r[31:28] <= data_in_r;
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8: begin
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- rtc_data_out_r[35:32] <= (data_in < 10)
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- ? data_in
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- : data_in - 10;
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- rtc_data_out_r[39:36] <= data_in < 10 ? 0 : 1;
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+ rtc_data_out_r[35:32] <= (data_in_r < 10)
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+ ? data_in_r
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+ : data_in_r - 10;
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+ rtc_data_out_r[39:36] <= data_in_r < 10 ? 0 : 1;
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end
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- 9: rtc_data_out_r[43:40] <= data_in;
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- 10: rtc_data_out_r[47:44] <= data_in;
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+ 9: rtc_data_out_r[43:40] <= data_in_r;
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+ 10: rtc_data_out_r[47:44] <= data_in_r;
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11: begin
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- rtc_data_out_r[51:48] <= (data_in < 10)
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- ? data_in
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- : data_in - 10;
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- rtc_data_out_r[55:52] <= data_in < 10 ? 1 : 2;
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+ rtc_data_out_r[51:48] <= (data_in_r < 10)
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+ ? data_in_r
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+ : data_in_r - 10;
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+ rtc_data_out_r[55:52] <= data_in_r < 10 ? 1 : 2;
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end
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endcase
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mode_r <= SRTC_WRITE2;
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- we_countdown_r <= 5;
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+ we_countdown_r <= 4;
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rtc_we_r <= 1;
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end
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end
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endcase
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endcase
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end else if(reg_oe_falling && enable) begin
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- case (addr_in)
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+ case (addr_in_r[0])
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1'b0: // read data register
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if(mode_r == SRTC_READ) begin
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case(rtc_ptr)
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@@ -171,18 +179,25 @@ always @(posedge clkin) begin
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+ (rtc_data_r[55:52] << 1)
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+ (rtc_data_r[55:52] << 3) - 10;
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12: data_out_r <= rtc_data_r[59:56];
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+// 14: mode_r <= SRTC_IDLE;
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15: begin
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rtc_data_r <= rtc_data_in;
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data_out_r <= 8'h0f;
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end
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- default: data_out_r <= 8'h0f;
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- endcase
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+ default: data_out_r <= 8'h0f;
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+ endcase
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rtc_ptr <= rtc_ptr == 13 ? 15 : rtc_ptr + 1;
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end else begin
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data_out_r <= 8'h00;
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end
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// 1'b1: // control register is write only
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endcase
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+ end else if(mode_r == SRTC_WRITE2) begin
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+ we_countdown_r <= we_countdown_r - 1;
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+ if (we_countdown_r == 3'b000) begin
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+ mode_r <= SRTC_WRITE;
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+ rtc_we_r <= 0;
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+ end
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end
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end
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