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@@ -305,7 +305,7 @@ cx4 snes_cx4 (
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.BUS_RDY(CX4_RDY),
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.cx4_active(cx4_active)
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);
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-
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+
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parameter MODE_SNES = 1'b0;
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parameter MODE_MCU = 1'b1;
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@@ -349,7 +349,7 @@ reg [7:0] ROM_DOUTr;
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assign SNES_DATA = (!SNES_READ)
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? (msu_enable ? MSU_SNES_DATA_OUT
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- :cx4_enable ? CX4_SNES_DATA_OUT
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+ :cx4_enable ? CX4_SNES_DATA_OUT
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:(cx4_active & cx4_vect_enable) ? CX4_SNES_DATA_OUT
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: SNES_DINr)
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: 8'bZ;
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@@ -381,14 +381,14 @@ assign MCU_RDY = RQ_MCU_RDYr;
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always @(posedge CLK2) begin
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if(MCU_RRQ) begin
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MCU_RD_PENDr <= 1'b1;
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- RQ_MCU_RDYr <= 1'b0;
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+ RQ_MCU_RDYr <= 1'b0;
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end else if(MCU_WRQ) begin
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MCU_WR_PENDr <= 1'b1;
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- RQ_MCU_RDYr <= 1'b0;
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+ RQ_MCU_RDYr <= 1'b0;
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end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
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MCU_RD_PENDr <= 1'b0;
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- MCU_WR_PENDr <= 1'b0;
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- RQ_MCU_RDYr <= 1'b1;
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+ MCU_WR_PENDr <= 1'b0;
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+ RQ_MCU_RDYr <= 1'b1;
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end
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end
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@@ -399,10 +399,10 @@ assign CX4_RDY = RQ_CX4_RDYr;
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always @(posedge CLK2) begin
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if(CX4_RRQ) begin
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CX4_RD_PENDr <= 1'b1;
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- RQ_CX4_RDYr <= 1'b0;
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+ RQ_CX4_RDYr <= 1'b0;
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end else if(STATE == ST_CX4_RD_WAIT && ST_MEM_DELAYr == 4'h0) begin
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CX4_RD_PENDr <= 1'b0;
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- RQ_CX4_RDYr <= 1'b1;
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+ RQ_CX4_RDYr <= 1'b1;
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end
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end
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@@ -416,126 +416,126 @@ always @(posedge CLK2) begin
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end else begin
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case(STATE)
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ST_IDLE: begin
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- ROM_ADDRr <= MAPPED_SNES_ADDR;
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+ ROM_ADDRr <= MAPPED_SNES_ADDR;
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if(CX4_RD_PENDr) begin
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STATE <= ST_CX4_RD_WAIT;
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ROM_ADDRr <= CX4_ADDR;
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ST_MEM_DELAYr <= ROM_RD_WAIT_CX4;
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end else if(~cx4_active && ~ASSERT_SNES_ADDR) begin
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- if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
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- else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR;
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+ if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
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+ else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR;
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else STATE <= ST_IDLE;
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end
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else STATE <= ST_IDLE;
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- end
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- ST_SNES_RD_ADDR: begin
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- STATE <= ST_SNES_RD_WAIT;
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- ST_MEM_DELAYr <= ROM_RD_WAIT;
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- end
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- ST_SNES_RD_WAIT: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END;
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- else STATE <= ST_SNES_RD_WAIT;
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- if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
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- else SNES_DINr <= ROM_DATA[15:8];
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- end
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- ST_SNES_RD_END: begin
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- STATE <= ST_IDLE;
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- if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
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- else SNES_DINr <= ROM_DATA[15:8];
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- end
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+ end
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+ ST_SNES_RD_ADDR: begin
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+ STATE <= ST_SNES_RD_WAIT;
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+ ST_MEM_DELAYr <= ROM_RD_WAIT;
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+ end
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+ ST_SNES_RD_WAIT: begin
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+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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+ if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END;
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+ else STATE <= ST_SNES_RD_WAIT;
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+ if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
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+ else SNES_DINr <= ROM_DATA[15:8];
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+ end
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+ ST_SNES_RD_END: begin
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+ STATE <= ST_IDLE;
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+ if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
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+ else SNES_DINr <= ROM_DATA[15:8];
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+ end
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ST_SNES_WR_ADDR: begin
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ROM_WEr <= (!IS_WRITABLE);
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snes_wr_cycle <= 1'b1;
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- STATE <= ST_SNES_WR_WAIT1;
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- ST_MEM_DELAYr <= ROM_WR_WAIT1;
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- end
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- ST_SNES_WR_WAIT1: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA;
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- else STATE <= ST_SNES_WR_WAIT1;
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- end
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- ST_SNES_WR_DATA: begin
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+ STATE <= ST_SNES_WR_WAIT1;
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+ ST_MEM_DELAYr <= ROM_WR_WAIT1;
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+ end
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+ ST_SNES_WR_WAIT1: begin
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+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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+ if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA;
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+ else STATE <= ST_SNES_WR_WAIT1;
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+ end
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+ ST_SNES_WR_DATA: begin
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ROM_DOUTr <= SNES_DATA;
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- ST_MEM_DELAYr <= ROM_WR_WAIT2;
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- STATE <= ST_SNES_WR_WAIT2;
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- end
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+ ST_MEM_DELAYr <= ROM_WR_WAIT2;
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+ STATE <= ST_SNES_WR_WAIT2;
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+ end
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ST_SNES_WR_WAIT2: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END;
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- else STATE <= ST_SNES_WR_WAIT2;
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- end
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- ST_SNES_WR_END: begin
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- STATE <= ST_IDLE;
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- ROM_WEr <= 1'b1;
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- snes_wr_cycle <= 1'b0;
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- end
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- ST_MCU_RD_ADDR: begin
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- ROM_ADDRr <= MCU_ADDR;
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- STATE <= ST_MCU_RD_WAIT;
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- ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
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- end
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- ST_MCU_RD_WAIT: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) begin
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- STATE <= ST_MCU_RD_WAIT2;
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+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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+ if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END;
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+ else STATE <= ST_SNES_WR_WAIT2;
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+ end
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+ ST_SNES_WR_END: begin
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+ STATE <= ST_IDLE;
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+ ROM_WEr <= 1'b1;
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+ snes_wr_cycle <= 1'b0;
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+ end
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+ ST_MCU_RD_ADDR: begin
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+ ROM_ADDRr <= MCU_ADDR;
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+ STATE <= ST_MCU_RD_WAIT;
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+ ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
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+ end
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+ ST_MCU_RD_WAIT: begin
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+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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+ if(ST_MEM_DELAYr == 4'h0) begin
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+ STATE <= ST_MCU_RD_WAIT2;
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ST_MEM_DELAYr <= 4'h2;
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if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0];
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else MCU_DINr <= ROM_DATA[15:8];
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- end
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- else STATE <= ST_MCU_RD_WAIT;
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+ end
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+ else STATE <= ST_MCU_RD_WAIT;
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end
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- ST_MCU_RD_WAIT2: begin
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+ ST_MCU_RD_WAIT2: begin
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ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) begin
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- STATE <= ST_MCU_RD_END;
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- end else STATE <= ST_MCU_RD_WAIT2;
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- end
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- ST_MCU_RD_END: begin
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- STATE <= ST_IDLE;
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- end
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- ST_MCU_WR_ADDR: begin
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- ROM_ADDRr <= MCU_ADDR;
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- STATE <= ST_MCU_WR_WAIT;
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- ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
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- ROM_DOUTr <= MCU_DOUT;
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- ROM_WEr <= 1'b0;
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- end
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- ST_MCU_WR_WAIT: begin
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+ if(ST_MEM_DELAYr == 4'h0) begin
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+ STATE <= ST_MCU_RD_END;
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+ end else STATE <= ST_MCU_RD_WAIT2;
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+ end
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+ ST_MCU_RD_END: begin
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+ STATE <= ST_IDLE;
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+ end
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+ ST_MCU_WR_ADDR: begin
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+ ROM_ADDRr <= MCU_ADDR;
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+ STATE <= ST_MCU_WR_WAIT;
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+ ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
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+ ROM_DOUTr <= MCU_DOUT;
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+ ROM_WEr <= 1'b0;
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+ end
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+ ST_MCU_WR_WAIT: begin
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ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) begin
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+ if(ST_MEM_DELAYr == 4'h0) begin
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ROM_WEr <= 1'b1;
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- STATE <= ST_MCU_WR_WAIT2;
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- ST_MEM_DELAYr <= 4'h2;
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- end
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- else STATE <= ST_MCU_WR_WAIT;
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+ STATE <= ST_MCU_WR_WAIT2;
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+ ST_MEM_DELAYr <= 4'h2;
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+ end
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+ else STATE <= ST_MCU_WR_WAIT;
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end
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- ST_MCU_WR_WAIT2: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) begin
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+ ST_MCU_WR_WAIT2: begin
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+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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+ if(ST_MEM_DELAYr == 4'h0) begin
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STATE <= ST_MCU_WR_END;
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end else STATE <= ST_MCU_WR_WAIT2;
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- end
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- ST_MCU_WR_END: begin
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- STATE <= ST_IDLE;
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- end
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-
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- ST_CX4_RD_ADDR: begin
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- ROM_ADDRr <= CX4_ADDR;
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- STATE <= ST_CX4_RD_WAIT;
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- ST_MEM_DELAYr <= ROM_RD_WAIT_CX4;
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- end
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- ST_CX4_RD_WAIT: begin
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+ end
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+ ST_MCU_WR_END: begin
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+ STATE <= ST_IDLE;
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+ end
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+
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+ ST_CX4_RD_ADDR: begin
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+ ROM_ADDRr <= CX4_ADDR;
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+ STATE <= ST_CX4_RD_WAIT;
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+ ST_MEM_DELAYr <= ROM_RD_WAIT_CX4;
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+ end
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+ ST_CX4_RD_WAIT: begin
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ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) STATE <= ST_IDLE;
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- else STATE <= ST_CX4_RD_WAIT;
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- if(ROM_ADDR0) CX4_DINr <= ROM_DATA[7:0];
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- else CX4_DINr <= ROM_DATA[15:8];
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+ if(ST_MEM_DELAYr == 4'h0) STATE <= ST_IDLE;
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+ else STATE <= ST_CX4_RD_WAIT;
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+ if(ROM_ADDR0) CX4_DINr <= ROM_DATA[7:0];
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+ else CX4_DINr <= ROM_DATA[15:8];
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+ end
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+ ST_CX4_RD_END: begin
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+ STATE <= ST_IDLE;
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end
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- ST_CX4_RD_END: begin
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- STATE <= ST_IDLE;
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- end
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- endcase
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+ endcase
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end
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end
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