main.v 16 KB

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  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: main
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Master Control FSM
  13. //
  14. // Dependencies: address
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module main(
  22. /* input clock */
  23. input CLKIN,
  24. /* SNES signals */
  25. input [23:0] SNES_ADDR,
  26. input SNES_READ,
  27. input SNES_WRITE,
  28. input SNES_CS,
  29. inout [7:0] SNES_DATA,
  30. input SNES_CPU_CLK,
  31. input SNES_REFRESH,
  32. output SNES_IRQ,
  33. output SNES_DATABUS_OE,
  34. output SNES_DATABUS_DIR,
  35. input SNES_SYSCLK,
  36. /* SRAM signals */
  37. /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
  38. inout [15:0] ROM_DATA,
  39. output [22:0] ROM_ADDR,
  40. output ROM_CE,
  41. output ROM_OE,
  42. output ROM_WE,
  43. output ROM_BHE,
  44. output ROM_BLE,
  45. /* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
  46. inout [7:0] RAM_DATA,
  47. output [18:0] RAM_ADDR,
  48. output RAM_CE,
  49. output RAM_OE,
  50. output RAM_WE,
  51. /* MCU signals */
  52. input SPI_MOSI,
  53. inout SPI_MISO,
  54. input SPI_SS,
  55. inout SPI_SCK,
  56. input MCU_OVR,
  57. output MCU_RDY,
  58. output DAC_MCLK,
  59. output DAC_LRCK,
  60. output DAC_SDOUT,
  61. /* SD signals */
  62. input [3:0] SD_DAT,
  63. inout SD_CMD,
  64. inout SD_CLK,
  65. /* debug */
  66. output p113_out
  67. );
  68. wire [7:0] spi_cmd_data;
  69. wire [7:0] spi_param_data;
  70. wire [7:0] spi_input_data;
  71. wire [31:0] spi_byte_cnt;
  72. wire [2:0] spi_bit_cnt;
  73. wire [23:0] MCU_ADDR;
  74. wire [2:0] MAPPER;
  75. wire [23:0] SAVERAM_MASK;
  76. wire [23:0] ROM_MASK;
  77. wire [7:0] SD_DMA_SRAM_DATA;
  78. wire [1:0] SD_DMA_TGT;
  79. wire [10:0] SD_DMA_PARTIAL_START;
  80. wire [10:0] SD_DMA_PARTIAL_END;
  81. wire [10:0] dac_addr;
  82. //wire [7:0] dac_volume;
  83. wire [7:0] msu_volumerq_out;
  84. wire [6:0] msu_status_out;
  85. wire [31:0] msu_addressrq_out;
  86. wire [15:0] msu_trackrq_out;
  87. wire [13:0] msu_write_addr;
  88. wire [13:0] msu_ptr_addr;
  89. wire [7:0] MSU_SNES_DATA_IN;
  90. wire [7:0] MSU_SNES_DATA_OUT;
  91. wire [5:0] msu_status_reset_bits;
  92. wire [5:0] msu_status_set_bits;
  93. wire [7:0] CX4_SNES_DATA_IN;
  94. wire [7:0] CX4_SNES_DATA_OUT;
  95. wire [23:0] MAPPED_SNES_ADDR;
  96. wire ROM_ADDR0;
  97. wire [23:0] cx4_datrom_data;
  98. wire [9:0] cx4_datrom_addr;
  99. wire cx4_datrom_we;
  100. sd_dma snes_sd_dma(
  101. .CLK(CLK2),
  102. .SD_DAT(SD_DAT),
  103. .SD_CLK(SD_CLK),
  104. .SD_DMA_EN(SD_DMA_EN),
  105. .SD_DMA_STATUS(SD_DMA_STATUS),
  106. .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
  107. .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
  108. .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  109. .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  110. .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  111. .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END)
  112. );
  113. wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
  114. dac snes_dac(
  115. .clkin(CLK2),
  116. .sysclk(SNES_SYSCLK),
  117. .mclk(DAC_MCLK),
  118. .lrck(DAC_LRCK),
  119. .sdout(DAC_SDOUT),
  120. .we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
  121. .pgm_address(dac_addr),
  122. .pgm_data(SD_DMA_SRAM_DATA),
  123. .DAC_STATUS(DAC_STATUS),
  124. .volume(msu_volumerq_out),
  125. .vol_latch(msu_volume_latch_out),
  126. .play(dac_play),
  127. .reset(dac_reset)
  128. );
  129. msu snes_msu (
  130. .clkin(CLK2),
  131. .enable(msu_enable),
  132. .pgm_address(msu_write_addr),
  133. .pgm_data(SD_DMA_SRAM_DATA),
  134. .pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
  135. .reg_addr(SNES_ADDR[2:0]),
  136. .reg_data_in(MSU_SNES_DATA_IN),
  137. .reg_data_out(MSU_SNES_DATA_OUT),
  138. .reg_oe(SNES_READ),
  139. .reg_we(SNES_WRITE),
  140. .status_out(msu_status_out),
  141. .volume_out(msu_volumerq_out),
  142. .volume_latch_out(msu_volume_latch_out),
  143. .addr_out(msu_addressrq_out),
  144. .track_out(msu_trackrq_out),
  145. .status_reset_bits(msu_status_reset_bits),
  146. .status_set_bits(msu_status_set_bits),
  147. .status_reset_we(msu_status_reset_we),
  148. .msu_address_ext(msu_ptr_addr),
  149. .msu_address_ext_write(msu_addr_reset)
  150. );
  151. spi snes_spi(
  152. .clk(CLK2),
  153. .MOSI(SPI_MOSI),
  154. .MISO(SPI_MISO),
  155. .SSEL(SPI_SS),
  156. .SCK(SPI_SCK),
  157. .cmd_ready(spi_cmd_ready),
  158. .param_ready(spi_param_ready),
  159. .cmd_data(spi_cmd_data),
  160. .param_data(spi_param_data),
  161. .endmessage(spi_endmessage),
  162. .startmessage(spi_startmessage),
  163. .input_data(spi_input_data),
  164. .byte_cnt(spi_byte_cnt),
  165. .bit_cnt(spi_bit_cnt)
  166. );
  167. reg [7:0] MCU_DINr;
  168. wire [7:0] MCU_DOUT;
  169. mcu_cmd snes_mcu_cmd(
  170. .clk(CLK2),
  171. .snes_sysclk(SNES_SYSCLK),
  172. .cmd_ready(spi_cmd_ready),
  173. .param_ready(spi_param_ready),
  174. .cmd_data(spi_cmd_data),
  175. .param_data(spi_param_data),
  176. .mcu_mapper(MAPPER),
  177. .mcu_write(MCU_WRITE),
  178. .mcu_data_in(MCU_DINr),
  179. .mcu_data_out(MCU_DOUT),
  180. .spi_byte_cnt(spi_byte_cnt),
  181. .spi_bit_cnt(spi_bit_cnt),
  182. .spi_data_out(spi_input_data),
  183. .addr_out(MCU_ADDR),
  184. .saveram_mask_out(SAVERAM_MASK),
  185. .rom_mask_out(ROM_MASK),
  186. .SD_DMA_EN(SD_DMA_EN),
  187. .SD_DMA_STATUS(SD_DMA_STATUS),
  188. .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  189. .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
  190. .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
  191. .SD_DMA_TGT(SD_DMA_TGT),
  192. .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  193. .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  194. .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
  195. .dac_addr_out(dac_addr),
  196. .DAC_STATUS(DAC_STATUS),
  197. // .dac_volume_out(dac_volume),
  198. // .dac_volume_latch_out(dac_vol_latch),
  199. .dac_play_out(dac_play),
  200. .dac_reset_out(dac_reset),
  201. .msu_addr_out(msu_write_addr),
  202. .MSU_STATUS(msu_status_out),
  203. .msu_status_reset_out(msu_status_reset_bits),
  204. .msu_status_set_out(msu_status_set_bits),
  205. .msu_status_reset_we(msu_status_reset_we),
  206. .msu_volumerq(msu_volumerq_out),
  207. .msu_addressrq(msu_addressrq_out),
  208. .msu_trackrq(msu_trackrq_out),
  209. .msu_ptr_out(msu_ptr_addr),
  210. .msu_reset_out(msu_addr_reset),
  211. .mcu_rrq(MCU_RRQ),
  212. .mcu_wrq(MCU_WRQ),
  213. .mcu_rq_rdy(MCU_RDY),
  214. .use_msu1(use_msu1),
  215. .cx4_datrom_addr_out(cx4_datrom_addr),
  216. .cx4_datrom_data_out(cx4_datrom_data),
  217. .cx4_datrom_we_out(cx4_datrom_we),
  218. .cx4_reset_out(cx4_reset)
  219. );
  220. wire [7:0] DCM_STATUS;
  221. // dcm1: dfs 4x
  222. my_dcm snes_dcm(
  223. .CLKIN(CLKIN),
  224. .CLKFX(CLK2),
  225. .LOCKED(DCM_LOCKED),
  226. .RST(DCM_RST),
  227. .STATUS(DCM_STATUS)
  228. );
  229. assign DCM_RST=0;
  230. reg [5:0] SNES_READr;
  231. reg [5:0] SNES_WRITEr;
  232. reg [5:0] SNES_CPU_CLKr;
  233. wire SNES_RD_start = (SNES_READr == 6'b111110);
  234. wire SNES_WR_start = (SNES_WRITEr == 6'b111110);
  235. wire SNES_cycle_start = (SNES_CPU_CLKr[5:0] == 6'b000001);
  236. wire SNES_cycle_end = (SNES_CPU_CLKr[5:0] == 6'b111110);
  237. always @(posedge CLK2) begin
  238. SNES_READr <= {SNES_READr[4:0], SNES_READ};
  239. SNES_WRITEr <= {SNES_WRITEr[4:0], SNES_WRITE};
  240. SNES_CPU_CLKr <= {SNES_CPU_CLKr[4:0], SNES_CPU_CLK};
  241. end
  242. address snes_addr(
  243. .CLK(CLK2),
  244. .MAPPER(MAPPER),
  245. .SNES_ADDR(SNES_ADDR), // requested address from SNES
  246. .SNES_CS(SNES_CS),
  247. .ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
  248. .ROM_SEL(ROM_SEL), // which SRAM unit to access
  249. .IS_SAVERAM(IS_SAVERAM),
  250. .IS_ROM(IS_ROM),
  251. .IS_WRITABLE(IS_WRITABLE),
  252. .SAVERAM_MASK(SAVERAM_MASK),
  253. .ROM_MASK(ROM_MASK),
  254. .use_msu1(use_msu1),
  255. //MSU-1
  256. .msu_enable(msu_enable),
  257. //CX4
  258. .cx4_enable(cx4_enable),
  259. .cx4_vect_enable(cx4_vect_enable)
  260. );
  261. reg [7:0] CX4_DINr;
  262. wire [23:0] CX4_ADDR;
  263. cx4 snes_cx4 (
  264. .DI(CX4_SNES_DATA_IN),
  265. .DO(CX4_SNES_DATA_OUT),
  266. .ADDR(SNES_ADDR[12:0]),
  267. .CS(cx4_enable),
  268. .SNES_VECT_EN(cx4_vect_enable),
  269. .nRD(SNES_READ),
  270. .nWR(SNES_WRITE),
  271. .CLK(CLK2),
  272. .DATROM_DI(cx4_datrom_data),
  273. .DATROM_WE(cx4_datrom_we),
  274. .DATROM_ADDR(cx4_datrom_addr),
  275. .BUS_DI(CX4_DINr),
  276. .BUS_ADDR(CX4_ADDR),
  277. .BUS_RRQ(CX4_RRQ),
  278. .BUS_RDY(CX4_RDY),
  279. .cx4_active(cx4_active)
  280. );
  281. parameter MODE_SNES = 1'b0;
  282. parameter MODE_MCU = 1'b1;
  283. parameter ST_IDLE = 21'b000000000000000000001;
  284. parameter ST_SNES_RD_ADDR = 21'b000000000000000000010;
  285. parameter ST_SNES_RD_WAIT = 21'b000000000000000000100;
  286. parameter ST_SNES_RD_END = 21'b000000000000000001000;
  287. parameter ST_SNES_WR_ADDR = 21'b000000000000000010000;
  288. parameter ST_SNES_WR_WAIT1= 21'b000000000000000100000;
  289. parameter ST_SNES_WR_DATA = 21'b000000000000001000000;
  290. parameter ST_SNES_WR_WAIT2= 21'b000000000000010000000;
  291. parameter ST_SNES_WR_END = 21'b000000000000100000000;
  292. parameter ST_MCU_RD_ADDR = 21'b000000000001000000000;
  293. parameter ST_MCU_RD_WAIT = 21'b000000000010000000000;
  294. parameter ST_MCU_RD_WAIT2 = 21'b000000000100000000000;
  295. parameter ST_MCU_RD_END = 21'b000000001000000000000;
  296. parameter ST_MCU_WR_ADDR = 21'b000000010000000000000;
  297. parameter ST_MCU_WR_WAIT = 21'b000000100000000000000;
  298. parameter ST_MCU_WR_WAIT2 = 21'b000001000000000000000;
  299. parameter ST_MCU_WR_END = 21'b000010000000000000000;
  300. parameter ST_CX4_RD_ADDR = 21'b000100000000000000000;
  301. parameter ST_CX4_RD_WAIT = 21'b001000000000000000000;
  302. parameter ST_CX4_RD_WAIT2 = 21'b010000000000000000000;
  303. parameter ST_CX4_RD_END = 21'b100000000000000000000;
  304. parameter ROM_RD_WAIT = 4'h4;
  305. parameter ROM_RD_WAIT_MCU = 4'h6;
  306. parameter ROM_WR_WAIT1 = 4'h2;
  307. parameter ROM_WR_WAIT2 = 4'h3;
  308. parameter ROM_WR_WAIT_MCU = 4'h6;
  309. parameter ROM_RD_WAIT_CX4 = 4'h6;
  310. reg [20:0] STATE;
  311. initial STATE = ST_IDLE;
  312. assign MSU_SNES_DATA_IN = SNES_DATA;
  313. assign CX4_SNES_DATA_IN = SNES_DATA;
  314. reg [7:0] SNES_DINr;
  315. reg [7:0] ROM_DOUTr;
  316. assign SNES_DATA = (!SNES_READ)
  317. ? (msu_enable ? MSU_SNES_DATA_OUT
  318. :cx4_enable ? CX4_SNES_DATA_OUT
  319. :(cx4_active & cx4_vect_enable) ? CX4_SNES_DATA_OUT
  320. : SNES_DINr)
  321. : 8'bZ;
  322. reg [3:0] ST_MEM_DELAYr;
  323. reg MCU_RD_PENDr;
  324. reg MCU_WR_PENDr;
  325. reg CX4_RD_PENDr;
  326. reg [23:0] ROM_ADDRr;
  327. reg NEED_SNES_ADDRr;
  328. always @(posedge CLK2) begin
  329. if(SNES_cycle_end) NEED_SNES_ADDRr <= 1'b1;
  330. else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0;
  331. end
  332. wire IS_CART = IS_ROM | IS_SAVERAM | IS_WRITABLE;
  333. wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr & IS_CART & ~cx4_active;
  334. assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
  335. assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
  336. reg ROM_WEr;
  337. initial ROM_WEr = 1'b1;
  338. reg RQ_MCU_RDYr;
  339. initial RQ_MCU_RDYr = 1'b1;
  340. assign MCU_RDY = RQ_MCU_RDYr;
  341. always @(posedge CLK2) begin
  342. if(MCU_RRQ) begin
  343. MCU_RD_PENDr <= 1'b1;
  344. RQ_MCU_RDYr <= 1'b0;
  345. end else if(MCU_WRQ) begin
  346. MCU_WR_PENDr <= 1'b1;
  347. RQ_MCU_RDYr <= 1'b0;
  348. end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
  349. MCU_RD_PENDr <= 1'b0;
  350. MCU_WR_PENDr <= 1'b0;
  351. RQ_MCU_RDYr <= 1'b1;
  352. end
  353. end
  354. reg RQ_CX4_RDYr;
  355. initial RQ_CX4_RDYr = 1'b1;
  356. assign CX4_RDY = RQ_CX4_RDYr;
  357. always @(posedge CLK2) begin
  358. if(CX4_RRQ) begin
  359. CX4_RD_PENDr <= 1'b1;
  360. RQ_CX4_RDYr <= 1'b0;
  361. end else if(STATE == ST_CX4_RD_WAIT && ST_MEM_DELAYr == 4'h0) begin
  362. CX4_RD_PENDr <= 1'b0;
  363. RQ_CX4_RDYr <= 1'b1;
  364. end
  365. end
  366. reg snes_wr_cycle;
  367. always @(posedge CLK2) begin
  368. if(SNES_cycle_start & IS_CART & ~cx4_active) begin
  369. STATE <= ST_SNES_RD_ADDR;
  370. end else if(SNES_WR_start & IS_CART & ~cx4_active) begin
  371. STATE <= ST_SNES_WR_ADDR;
  372. end else begin
  373. case(STATE)
  374. ST_IDLE: begin
  375. ROM_ADDRr <= MAPPED_SNES_ADDR;
  376. if(CX4_RD_PENDr) begin
  377. STATE <= ST_CX4_RD_WAIT;
  378. ROM_ADDRr <= CX4_ADDR;
  379. ST_MEM_DELAYr <= ROM_RD_WAIT_CX4;
  380. end else if(~cx4_active && ~ASSERT_SNES_ADDR) begin
  381. if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
  382. else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR;
  383. else STATE <= ST_IDLE;
  384. end
  385. else STATE <= ST_IDLE;
  386. end
  387. ST_SNES_RD_ADDR: begin
  388. STATE <= ST_SNES_RD_WAIT;
  389. ST_MEM_DELAYr <= ROM_RD_WAIT;
  390. end
  391. ST_SNES_RD_WAIT: begin
  392. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  393. if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END;
  394. else STATE <= ST_SNES_RD_WAIT;
  395. if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
  396. else SNES_DINr <= ROM_DATA[15:8];
  397. end
  398. ST_SNES_RD_END: begin
  399. STATE <= ST_IDLE;
  400. if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
  401. else SNES_DINr <= ROM_DATA[15:8];
  402. end
  403. ST_SNES_WR_ADDR: begin
  404. ROM_WEr <= (!IS_WRITABLE);
  405. snes_wr_cycle <= 1'b1;
  406. STATE <= ST_SNES_WR_WAIT1;
  407. ST_MEM_DELAYr <= ROM_WR_WAIT1;
  408. end
  409. ST_SNES_WR_WAIT1: begin
  410. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  411. if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA;
  412. else STATE <= ST_SNES_WR_WAIT1;
  413. end
  414. ST_SNES_WR_DATA: begin
  415. ROM_DOUTr <= SNES_DATA;
  416. ST_MEM_DELAYr <= ROM_WR_WAIT2;
  417. STATE <= ST_SNES_WR_WAIT2;
  418. end
  419. ST_SNES_WR_WAIT2: begin
  420. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  421. if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END;
  422. else STATE <= ST_SNES_WR_WAIT2;
  423. end
  424. ST_SNES_WR_END: begin
  425. STATE <= ST_IDLE;
  426. ROM_WEr <= 1'b1;
  427. snes_wr_cycle <= 1'b0;
  428. end
  429. ST_MCU_RD_ADDR: begin
  430. ROM_ADDRr <= MCU_ADDR;
  431. STATE <= ST_MCU_RD_WAIT;
  432. ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
  433. end
  434. ST_MCU_RD_WAIT: begin
  435. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  436. if(ST_MEM_DELAYr == 4'h0) begin
  437. STATE <= ST_MCU_RD_WAIT2;
  438. ST_MEM_DELAYr <= 4'h2;
  439. if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0];
  440. else MCU_DINr <= ROM_DATA[15:8];
  441. end
  442. else STATE <= ST_MCU_RD_WAIT;
  443. end
  444. ST_MCU_RD_WAIT2: begin
  445. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  446. if(ST_MEM_DELAYr == 4'h0) begin
  447. STATE <= ST_MCU_RD_END;
  448. end else STATE <= ST_MCU_RD_WAIT2;
  449. end
  450. ST_MCU_RD_END: begin
  451. STATE <= ST_IDLE;
  452. end
  453. ST_MCU_WR_ADDR: begin
  454. ROM_ADDRr <= MCU_ADDR;
  455. STATE <= ST_MCU_WR_WAIT;
  456. ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
  457. ROM_DOUTr <= MCU_DOUT;
  458. ROM_WEr <= 1'b0;
  459. end
  460. ST_MCU_WR_WAIT: begin
  461. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  462. if(ST_MEM_DELAYr == 4'h0) begin
  463. ROM_WEr <= 1'b1;
  464. STATE <= ST_MCU_WR_WAIT2;
  465. ST_MEM_DELAYr <= 4'h2;
  466. end
  467. else STATE <= ST_MCU_WR_WAIT;
  468. end
  469. ST_MCU_WR_WAIT2: begin
  470. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  471. if(ST_MEM_DELAYr == 4'h0) begin
  472. STATE <= ST_MCU_WR_END;
  473. end else STATE <= ST_MCU_WR_WAIT2;
  474. end
  475. ST_MCU_WR_END: begin
  476. STATE <= ST_IDLE;
  477. end
  478. ST_CX4_RD_ADDR: begin
  479. ROM_ADDRr <= CX4_ADDR;
  480. STATE <= ST_CX4_RD_WAIT;
  481. ST_MEM_DELAYr <= ROM_RD_WAIT_CX4;
  482. end
  483. ST_CX4_RD_WAIT: begin
  484. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  485. if(ST_MEM_DELAYr == 4'h0) STATE <= ST_IDLE;
  486. else STATE <= ST_CX4_RD_WAIT;
  487. if(ROM_ADDR0) CX4_DINr <= ROM_DATA[7:0];
  488. else CX4_DINr <= ROM_DATA[15:8];
  489. end
  490. ST_CX4_RD_END: begin
  491. STATE <= ST_IDLE;
  492. end
  493. endcase
  494. end
  495. end
  496. assign ROM_DATA[7:0] = ROM_ADDR0
  497. ?(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
  498. : (!ROM_WE ? ROM_DOUTr : 8'bZ)
  499. )
  500. :8'bZ;
  501. assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
  502. :(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
  503. : (!ROM_WE ? ROM_DOUTr : 8'bZ)
  504. );
  505. assign ROM_WE = SD_DMA_TO_ROM
  506. ?MCU_WRITE
  507. :ROM_WEr | (ASSERT_SNES_ADDR & ~snes_wr_cycle);
  508. // OE always active. Overridden by WE when needed.
  509. assign ROM_OE = 1'b0;
  510. assign ROM_CE = 1'b0;
  511. assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0;
  512. assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
  513. assign SNES_DATABUS_OE = msu_enable ? 1'b0 :
  514. cx4_enable ? 1'b0 :
  515. (cx4_active & cx4_vect_enable) ? 1'b0 :
  516. ((!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
  517. |(SNES_READ & SNES_WRITE)
  518. );
  519. assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
  520. assign IRQ_DIR = 1'b0;
  521. assign SNES_IRQ = 1'bZ;
  522. assign p113_out = 1'b0;
  523. endmodule