k3-j7200-main.dtsi 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for J7200 SoC Family Main Domain peripherals
  4. *
  5. * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
  6. */
  7. &cbass_main {
  8. msmc_ram: sram@70000000 {
  9. compatible = "mmio-sram";
  10. reg = <0x0 0x70000000 0x0 0x100000>;
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. ranges = <0x0 0x0 0x70000000 0x100000>;
  14. atf-sram@0 {
  15. reg = <0x0 0x20000>;
  16. };
  17. };
  18. gic500: interrupt-controller@1800000 {
  19. compatible = "arm,gic-v3";
  20. #address-cells = <2>;
  21. #size-cells = <2>;
  22. ranges;
  23. #interrupt-cells = <3>;
  24. interrupt-controller;
  25. reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
  26. <0x00 0x01900000 0x00 0x100000>; /* GICR */
  27. /* vcpumntirq: virtual CPU interface maintenance interrupt */
  28. interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  29. gic_its: msi-controller@1820000 {
  30. compatible = "arm,gic-v3-its";
  31. reg = <0x00 0x01820000 0x00 0x10000>;
  32. socionext,synquacer-pre-its = <0x1000000 0x400000>;
  33. msi-controller;
  34. #msi-cells = <1>;
  35. };
  36. };
  37. main_navss: navss@30000000 {
  38. compatible = "simple-mfd";
  39. #address-cells = <2>;
  40. #size-cells = <2>;
  41. ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
  42. secure_proxy_main: mailbox@32c00000 {
  43. compatible = "ti,am654-secure-proxy";
  44. #mbox-cells = <1>;
  45. reg-names = "target_data", "rt", "scfg";
  46. reg = <0x00 0x32c00000 0x00 0x100000>,
  47. <0x00 0x32400000 0x00 0x100000>,
  48. <0x00 0x32800000 0x00 0x100000>;
  49. interrupt-names = "rx_011";
  50. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  51. };
  52. };
  53. main_pmx0: pinmux@11c000 {
  54. compatible = "pinctrl-single";
  55. /* Proxy 0 addressing */
  56. reg = <0x0 0x11c000 0x0 0x2b4>;
  57. #pinctrl-cells = <1>;
  58. pinctrl-single,register-width = <32>;
  59. pinctrl-single,function-mask = <0xffffffff>;
  60. };
  61. main_uart0: serial@2800000 {
  62. compatible = "ti,j721e-uart", "ti,am654-uart";
  63. reg = <0x00 0x02800000 0x00 0x100>;
  64. reg-shift = <2>;
  65. reg-io-width = <4>;
  66. interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
  67. clock-frequency = <48000000>;
  68. current-speed = <115200>;
  69. power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
  70. clocks = <&k3_clks 146 2>;
  71. clock-names = "fclk";
  72. };
  73. main_uart1: serial@2810000 {
  74. compatible = "ti,j721e-uart", "ti,am654-uart";
  75. reg = <0x00 0x02810000 0x00 0x100>;
  76. reg-shift = <2>;
  77. reg-io-width = <4>;
  78. interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
  79. clock-frequency = <48000000>;
  80. current-speed = <115200>;
  81. power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
  82. clocks = <&k3_clks 278 2>;
  83. clock-names = "fclk";
  84. };
  85. main_uart2: serial@2820000 {
  86. compatible = "ti,j721e-uart", "ti,am654-uart";
  87. reg = <0x00 0x02820000 0x00 0x100>;
  88. reg-shift = <2>;
  89. reg-io-width = <4>;
  90. interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
  91. clock-frequency = <48000000>;
  92. current-speed = <115200>;
  93. power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
  94. clocks = <&k3_clks 279 2>;
  95. clock-names = "fclk";
  96. };
  97. main_uart3: serial@2830000 {
  98. compatible = "ti,j721e-uart", "ti,am654-uart";
  99. reg = <0x00 0x02830000 0x00 0x100>;
  100. reg-shift = <2>;
  101. reg-io-width = <4>;
  102. interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
  103. clock-frequency = <48000000>;
  104. current-speed = <115200>;
  105. power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
  106. clocks = <&k3_clks 280 2>;
  107. clock-names = "fclk";
  108. };
  109. main_uart4: serial@2840000 {
  110. compatible = "ti,j721e-uart", "ti,am654-uart";
  111. reg = <0x00 0x02840000 0x00 0x100>;
  112. reg-shift = <2>;
  113. reg-io-width = <4>;
  114. interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
  115. clock-frequency = <48000000>;
  116. current-speed = <115200>;
  117. power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
  118. clocks = <&k3_clks 281 2>;
  119. clock-names = "fclk";
  120. };
  121. main_uart5: serial@2850000 {
  122. compatible = "ti,j721e-uart", "ti,am654-uart";
  123. reg = <0x00 0x02850000 0x00 0x100>;
  124. reg-shift = <2>;
  125. reg-io-width = <4>;
  126. interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
  127. clock-frequency = <48000000>;
  128. current-speed = <115200>;
  129. power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
  130. clocks = <&k3_clks 282 2>;
  131. clock-names = "fclk";
  132. };
  133. main_uart6: serial@2860000 {
  134. compatible = "ti,j721e-uart", "ti,am654-uart";
  135. reg = <0x00 0x02860000 0x00 0x100>;
  136. reg-shift = <2>;
  137. reg-io-width = <4>;
  138. interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
  139. clock-frequency = <48000000>;
  140. current-speed = <115200>;
  141. power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
  142. clocks = <&k3_clks 283 2>;
  143. clock-names = "fclk";
  144. };
  145. main_uart7: serial@2870000 {
  146. compatible = "ti,j721e-uart", "ti,am654-uart";
  147. reg = <0x00 0x02870000 0x00 0x100>;
  148. reg-shift = <2>;
  149. reg-io-width = <4>;
  150. interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
  151. clock-frequency = <48000000>;
  152. current-speed = <115200>;
  153. power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
  154. clocks = <&k3_clks 284 2>;
  155. clock-names = "fclk";
  156. };
  157. main_uart8: serial@2880000 {
  158. compatible = "ti,j721e-uart", "ti,am654-uart";
  159. reg = <0x00 0x02880000 0x00 0x100>;
  160. reg-shift = <2>;
  161. reg-io-width = <4>;
  162. interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
  163. clock-frequency = <48000000>;
  164. current-speed = <115200>;
  165. power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
  166. clocks = <&k3_clks 285 2>;
  167. clock-names = "fclk";
  168. };
  169. main_uart9: serial@2890000 {
  170. compatible = "ti,j721e-uart", "ti,am654-uart";
  171. reg = <0x00 0x02890000 0x00 0x100>;
  172. reg-shift = <2>;
  173. reg-io-width = <4>;
  174. interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
  175. clock-frequency = <48000000>;
  176. current-speed = <115200>;
  177. power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
  178. clocks = <&k3_clks 286 2>;
  179. clock-names = "fclk";
  180. };
  181. main_sdhci0: sdhci@4f80000 {
  182. compatible = "ti,j721e-sdhci-8bit";
  183. reg = <0x0 0x04f80000 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>;
  184. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  185. power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
  186. clock-names = "clk_xin", "clk_ahb";
  187. clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;
  188. ti,otap-del-sel-legacy = <0x0>;
  189. ti,otap-del-sel-mmc-hs = <0x0>;
  190. ti,otap-del-sel-ddr52 = <0x6>;
  191. ti,otap-del-sel-hs200 = <0x8>;
  192. ti,otap-del-sel-hs400 = <0x0>;
  193. ti,strobe-sel = <0x77>;
  194. ti,trm-icp = <0x8>;
  195. bus-width = <8>;
  196. mmc-hs200-1_8v;
  197. mmc-ddr-1_8v;
  198. dma-coherent;
  199. };
  200. main_sdhci1: sdhci@4fb0000 {
  201. compatible = "ti,j721e-sdhci-4bit";
  202. reg = <0x0 0x04fb0000 0x0 0x260>, <0x0 0x4fb8000 0x0 0x134>;
  203. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  204. power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
  205. clock-names = "clk_xin", "clk_ahb";
  206. clocks = <&k3_clks 92 2>, <&k3_clks 92 1>;
  207. ti,otap-del-sel-legacy = <0x0>;
  208. ti,otap-del-sel-sd-hs = <0x0>;
  209. ti,otap-del-sel-sdr12 = <0xf>;
  210. ti,otap-del-sel-sdr25 = <0xf>;
  211. ti,otap-del-sel-sdr50 = <0xc>;
  212. ti,otap-del-sel-sdr104 = <0x5>;
  213. ti,otap-del-sel-ddr50 = <0xc>;
  214. dma-coherent;
  215. };
  216. main_i2c0: i2c@2000000 {
  217. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  218. reg = <0x0 0x2000000 0x0 0x100>;
  219. interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
  220. #address-cells = <1>;
  221. #size-cells = <0>;
  222. clock-names = "fck";
  223. clocks = <&k3_clks 187 1>;
  224. power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
  225. };
  226. main_i2c1: i2c@2010000 {
  227. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  228. reg = <0x0 0x2010000 0x0 0x100>;
  229. interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
  230. #address-cells = <1>;
  231. #size-cells = <0>;
  232. clock-names = "fck";
  233. clocks = <&k3_clks 188 1>;
  234. power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
  235. };
  236. main_i2c2: i2c@2020000 {
  237. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  238. reg = <0x0 0x2020000 0x0 0x100>;
  239. interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
  240. #address-cells = <1>;
  241. #size-cells = <0>;
  242. clock-names = "fck";
  243. clocks = <&k3_clks 189 1>;
  244. power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
  245. };
  246. main_i2c3: i2c@2030000 {
  247. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  248. reg = <0x0 0x2030000 0x0 0x100>;
  249. interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
  250. #address-cells = <1>;
  251. #size-cells = <0>;
  252. clock-names = "fck";
  253. clocks = <&k3_clks 190 1>;
  254. power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
  255. };
  256. main_i2c4: i2c@2040000 {
  257. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  258. reg = <0x0 0x2040000 0x0 0x100>;
  259. interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
  260. #address-cells = <1>;
  261. #size-cells = <0>;
  262. clock-names = "fck";
  263. clocks = <&k3_clks 191 1>;
  264. power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
  265. };
  266. main_i2c5: i2c@2050000 {
  267. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  268. reg = <0x0 0x2050000 0x0 0x100>;
  269. interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
  270. #address-cells = <1>;
  271. #size-cells = <0>;
  272. clock-names = "fck";
  273. clocks = <&k3_clks 192 1>;
  274. power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
  275. };
  276. main_i2c6: i2c@2060000 {
  277. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  278. reg = <0x0 0x2060000 0x0 0x100>;
  279. interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
  280. #address-cells = <1>;
  281. #size-cells = <0>;
  282. clock-names = "fck";
  283. clocks = <&k3_clks 193 1>;
  284. power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
  285. };
  286. usbss0: cdns_usb@4104000 {
  287. compatible = "ti,j721e-usb";
  288. reg = <0x00 0x4104000 0x00 0x100>;
  289. dma-coherent;
  290. power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
  291. clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
  292. clock-names = "usb2_refclk", "lpm_clk";
  293. assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
  294. assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
  295. #address-cells = <2>;
  296. #size-cells = <2>;
  297. ranges;
  298. usb0: usb@6000000 {
  299. compatible = "cdns,usb3";
  300. reg = <0x00 0x6000000 0x00 0x10000>,
  301. <0x00 0x6010000 0x00 0x10000>,
  302. <0x00 0x6020000 0x00 0x10000>;
  303. reg-names = "otg", "xhci", "dev";
  304. interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
  305. <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
  306. <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
  307. interrupt-names = "host",
  308. "peripheral",
  309. "otg";
  310. maximum-speed = "super-speed";
  311. dr_mode = "otg";
  312. };
  313. };
  314. main_r5fss0: r5fss@5c00000 {
  315. compatible = "ti,j7200-r5fss";
  316. lockstep-mode = <0>;
  317. #address-cells = <1>;
  318. #size-cells = <1>;
  319. ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
  320. <0x5d00000 0x00 0x5d00000 0x20000>;
  321. power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
  322. main_r5fss0_core0: r5f@5c00000 {
  323. compatible = "ti,j7200-r5f";
  324. reg = <0x5c00000 0x00010000>,
  325. <0x5c10000 0x00010000>;
  326. reg-names = "atcm", "btcm";
  327. ti,sci = <&dmsc>;
  328. ti,sci-dev-id = <245>;
  329. ti,sci-proc-ids = <0x06 0xFF>;
  330. resets = <&k3_reset 245 1>;
  331. firmware-name = "j7200-main-r5f0_0-fw";
  332. atcm-enable = <1>;
  333. btcm-enable = <1>;
  334. loczrama = <1>;
  335. };
  336. main_r5fss0_core1: r5f@5d00000 {
  337. compatible = "ti,j7200-r5f";
  338. reg = <0x5d00000 0x00008000>,
  339. <0x5d10000 0x00008000>;
  340. reg-names = "atcm", "btcm";
  341. ti,sci = <&dmsc>;
  342. ti,sci-dev-id = <246>;
  343. ti,sci-proc-ids = <0x07 0xFF>;
  344. resets = <&k3_reset 246 1>;
  345. firmware-name = "j7200-main-r5f0_1-fw";
  346. atcm-enable = <1>;
  347. btcm-enable = <1>;
  348. loczrama = <1>;
  349. };
  350. };
  351. };