// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for J7200 SoC Family Main Domain peripherals * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; reg = <0x0 0x70000000 0x0 0x100000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x70000000 0x100000>; atf-sram@0 { reg = <0x0 0x20000>; }; }; gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; #size-cells = <2>; ranges; #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ <0x00 0x01900000 0x00 0x100000>; /* GICR */ /* vcpumntirq: virtual CPU interface maintenance interrupt */ interrupts = ; gic_its: msi-controller@1820000 { compatible = "arm,gic-v3-its"; reg = <0x00 0x01820000 0x00 0x10000>; socionext,synquacer-pre-its = <0x1000000 0x400000>; msi-controller; #msi-cells = <1>; }; }; main_navss: navss@30000000 { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; secure_proxy_main: mailbox@32c00000 { compatible = "ti,am654-secure-proxy"; #mbox-cells = <1>; reg-names = "target_data", "rt", "scfg"; reg = <0x00 0x32c00000 0x00 0x100000>, <0x00 0x32400000 0x00 0x100000>, <0x00 0x32800000 0x00 0x100000>; interrupt-names = "rx_011"; interrupts = ; }; }; main_pmx0: pinmux@11c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x0 0x11c000 0x0 0x2b4>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 2>; clock-names = "fclk"; }; main_uart1: serial@2810000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 278 2>; clock-names = "fclk"; }; main_uart2: serial@2820000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 279 2>; clock-names = "fclk"; }; main_uart3: serial@2830000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02830000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 280 2>; clock-names = "fclk"; }; main_uart4: serial@2840000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02840000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 281 2>; clock-names = "fclk"; }; main_uart5: serial@2850000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02850000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 282 2>; clock-names = "fclk"; }; main_uart6: serial@2860000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02860000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 283 2>; clock-names = "fclk"; }; main_uart7: serial@2870000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02870000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 284 2>; clock-names = "fclk"; }; main_uart8: serial@2880000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02880000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 285 2>; clock-names = "fclk"; }; main_uart9: serial@2890000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02890000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 286 2>; clock-names = "fclk"; }; main_sdhci0: sdhci@4f80000 { compatible = "ti,j721e-sdhci-8bit"; reg = <0x0 0x04f80000 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>; interrupts = ; power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; clock-names = "clk_xin", "clk_ahb"; clocks = <&k3_clks 91 3>, <&k3_clks 91 0>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x6>; ti,otap-del-sel-hs200 = <0x8>; ti,otap-del-sel-hs400 = <0x0>; ti,strobe-sel = <0x77>; ti,trm-icp = <0x8>; bus-width = <8>; mmc-hs200-1_8v; mmc-ddr-1_8v; dma-coherent; }; main_sdhci1: sdhci@4fb0000 { compatible = "ti,j721e-sdhci-4bit"; reg = <0x0 0x04fb0000 0x0 0x260>, <0x0 0x4fb8000 0x0 0x134>; interrupts = ; power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; clock-names = "clk_xin", "clk_ahb"; clocks = <&k3_clks 92 2>, <&k3_clks 92 1>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-sdr104 = <0x5>; ti,otap-del-sel-ddr50 = <0xc>; dma-coherent; }; main_i2c0: i2c@2000000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x0 0x2000000 0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 187 1>; power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; }; main_i2c1: i2c@2010000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x0 0x2010000 0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 188 1>; power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; }; main_i2c2: i2c@2020000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x0 0x2020000 0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 189 1>; power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; }; main_i2c3: i2c@2030000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x0 0x2030000 0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 190 1>; power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; }; main_i2c4: i2c@2040000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x0 0x2040000 0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 191 1>; power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; }; main_i2c5: i2c@2050000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x0 0x2050000 0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 192 1>; power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; }; main_i2c6: i2c@2060000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x0 0x2060000 0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 193 1>; power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; }; usbss0: cdns_usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4104000 0x00 0x100>; dma-coherent; power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; clock-names = "usb2_refclk", "lpm_clk"; assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ #address-cells = <2>; #size-cells = <2>; ranges; usb0: usb@6000000 { compatible = "cdns,usb3"; reg = <0x00 0x6000000 0x00 0x10000>, <0x00 0x6010000 0x00 0x10000>, <0x00 0x6020000 0x00 0x10000>; reg-names = "otg", "xhci", "dev"; interrupts = , /* irq.0 */ , /* irq.6 */ ; /* otgirq.0 */ interrupt-names = "host", "peripheral", "otg"; maximum-speed = "super-speed"; dr_mode = "otg"; }; }; main_r5fss0: r5fss@5c00000 { compatible = "ti,j7200-r5fss"; lockstep-mode = <0>; #address-cells = <1>; #size-cells = <1>; ranges = <0x5c00000 0x00 0x5c00000 0x20000>, <0x5d00000 0x00 0x5d00000 0x20000>; power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; main_r5fss0_core0: r5f@5c00000 { compatible = "ti,j7200-r5f"; reg = <0x5c00000 0x00010000>, <0x5c10000 0x00010000>; reg-names = "atcm", "btcm"; ti,sci = <&dmsc>; ti,sci-dev-id = <245>; ti,sci-proc-ids = <0x06 0xFF>; resets = <&k3_reset 245 1>; firmware-name = "j7200-main-r5f0_0-fw"; atcm-enable = <1>; btcm-enable = <1>; loczrama = <1>; }; main_r5fss0_core1: r5f@5d00000 { compatible = "ti,j7200-r5f"; reg = <0x5d00000 0x00008000>, <0x5d10000 0x00008000>; reg-names = "atcm", "btcm"; ti,sci = <&dmsc>; ti,sci-dev-id = <246>; ti,sci-proc-ids = <0x07 0xFF>; resets = <&k3_reset 246 1>; firmware-name = "j7200-main-r5f0_1-fw"; atcm-enable = <1>; btcm-enable = <1>; loczrama = <1>; }; }; };