spl.c 6.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017-2018 NXP
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <image.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <spl.h>
  11. #include <fsl_esdhc.h>
  12. #include <asm/io.h>
  13. #include <asm/gpio.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/sci/sci.h>
  16. #include <asm/arch/imx8-pins.h>
  17. #include <asm/arch/iomux.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
  20. (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  21. (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  22. (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  23. #define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
  24. (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  25. (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  26. (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  27. #define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
  28. (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  29. (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
  30. (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  31. #define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
  32. (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  33. (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
  34. (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  35. #define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
  36. (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  37. (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  38. (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  39. #define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
  40. (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  41. (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  42. (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  43. #define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
  44. (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  45. (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
  46. (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  47. #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
  48. (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  49. (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  50. (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  51. #ifdef CONFIG_FSL_ESDHC
  52. #define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
  53. #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
  54. static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
  55. {USDHC1_BASE_ADDR, 0, 8},
  56. {USDHC2_BASE_ADDR, 0, 4},
  57. {USDHC3_BASE_ADDR, 0, 4},
  58. };
  59. static iomux_cfg_t emmc0[] = {
  60. SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
  61. SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  62. SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  63. SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  64. SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  65. SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  66. SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  67. SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  68. SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  69. SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  70. SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  71. SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  72. };
  73. static iomux_cfg_t usdhc2_sd[] = {
  74. SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
  75. SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  76. SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  77. SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  78. SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  79. SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  80. SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  81. SC_P_USDHC2_WP | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  82. SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  83. };
  84. int board_mmc_init(struct bd_info *bis)
  85. {
  86. int i, ret;
  87. /*
  88. * According to the board_mmc_init() the following map is done:
  89. * (U-Boot device node) (Physical Port)
  90. * mmc0 USDHC1
  91. * mmc1 USDHC2
  92. * mmc2 USDHC3
  93. */
  94. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  95. switch (i) {
  96. case 0:
  97. ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
  98. if (ret != SC_ERR_NONE)
  99. return ret;
  100. imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
  101. init_clk_usdhc(0);
  102. usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  103. break;
  104. case 1:
  105. ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
  106. if (ret != SC_ERR_NONE)
  107. return ret;
  108. ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
  109. if (ret != SC_ERR_NONE)
  110. return ret;
  111. imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
  112. init_clk_usdhc(2);
  113. usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  114. gpio_request(USDHC2_CD_GPIO, "sd2_cd");
  115. gpio_direction_input(USDHC2_CD_GPIO);
  116. break;
  117. default:
  118. printf("Warning: you configured more USDHC controllers"
  119. "(%d) than supported by the board\n", i + 1);
  120. return 0;
  121. }
  122. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  123. if (ret) {
  124. printf("Warning: failed to initialize mmc dev %d\n", i);
  125. return ret;
  126. }
  127. }
  128. return 0;
  129. }
  130. int board_mmc_getcd(struct mmc *mmc)
  131. {
  132. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  133. int ret = 0;
  134. switch (cfg->esdhc_base) {
  135. case USDHC1_BASE_ADDR:
  136. ret = 1;
  137. break;
  138. case USDHC2_BASE_ADDR:
  139. ret = !gpio_get_value(USDHC1_CD_GPIO);
  140. break;
  141. case USDHC3_BASE_ADDR:
  142. ret = !gpio_get_value(USDHC2_CD_GPIO);
  143. break;
  144. }
  145. return ret;
  146. }
  147. #endif /* CONFIG_FSL_ESDHC */
  148. void spl_board_init(void)
  149. {
  150. #if defined(CONFIG_SPL_SPI_SUPPORT)
  151. if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
  152. if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) {
  153. puts("Warning: failed to initialize FSPI0\n");
  154. }
  155. }
  156. #endif
  157. puts("Normal Boot\n");
  158. }
  159. void spl_board_prepare_for_boot(void)
  160. {
  161. #if defined(CONFIG_SPL_SPI_SUPPORT)
  162. if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
  163. if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) {
  164. puts("Warning: failed to turn off FSPI0\n");
  165. }
  166. }
  167. #endif
  168. }
  169. #ifdef CONFIG_SPL_LOAD_FIT
  170. int board_fit_config_name_match(const char *name)
  171. {
  172. /* Just empty function now - can't decide what to choose */
  173. debug("%s: %s\n", __func__, name);
  174. return 0;
  175. }
  176. #endif
  177. void board_init_f(ulong dummy)
  178. {
  179. /* Clear global data */
  180. memset((void *)gd, 0, sizeof(gd_t));
  181. arch_cpu_init();
  182. board_early_init_f();
  183. timer_init();
  184. preloader_console_init();
  185. /* Clear the BSS. */
  186. memset(__bss_start, 0, __bss_end - __bss_start);
  187. board_init_r(NULL, 0);
  188. }