tlb.c 3.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/mmu.h>
  7. struct fsl_e_tlb_entry tlb_table[] = {
  8. /* TLB 0 - for temp stack in cache */
  9. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  10. CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  11. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  12. 0, 0, BOOKE_PAGESZ_4K, 0),
  13. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
  14. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  15. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  16. 0, 0, BOOKE_PAGESZ_4K, 0),
  17. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
  18. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  19. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  20. 0, 0, BOOKE_PAGESZ_4K, 0),
  21. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
  22. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  23. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  24. 0, 0, BOOKE_PAGESZ_4K, 0),
  25. /* TLB 1 */
  26. /* *I*** - Covers boot page */
  27. SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  28. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
  29. 0, 0, BOOKE_PAGESZ_4K, 1),
  30. /* *I*G* - CCSRBAR */
  31. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  32. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  33. 0, 1, BOOKE_PAGESZ_1M, 1),
  34. #ifndef CONFIG_SPL_BUILD
  35. /* W**G* - Flash/promjet, localbus */
  36. /* This will be changed to *I*G* after relocation to RAM. */
  37. SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  38. MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  39. 0, 2, BOOKE_PAGESZ_64M, 1),
  40. #ifdef CONFIG_PCI
  41. /* *I*G* - PCI memory 1.5G */
  42. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  43. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  44. 0, 3, BOOKE_PAGESZ_1G, 1),
  45. /* *I*G* - PCI I/O effective: 192K */
  46. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  47. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  48. 0, 4, BOOKE_PAGESZ_256K, 1),
  49. #endif
  50. #ifdef CONFIG_VSC7385_ENET
  51. /* *I*G - VSC7385 Switch */
  52. SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
  53. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  54. 0, 5, BOOKE_PAGESZ_1M, 1),
  55. #endif
  56. SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
  57. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  58. 0, 6, BOOKE_PAGESZ_1M, 1),
  59. SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,
  60. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  61. 0, 10, BOOKE_PAGESZ_64K, 1),
  62. #endif /* not SPL */
  63. #ifdef CONFIG_SYS_NAND_BASE
  64. /* *I*G - NAND */
  65. SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  66. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  67. 0, 7, BOOKE_PAGESZ_1M, 1),
  68. #endif
  69. #if defined(CONFIG_SYS_RAMBOOT) || \
  70. (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
  71. /* *I*G - eSDHC/eSPI/NAND boot */
  72. SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  73. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
  74. 0, 8, BOOKE_PAGESZ_1G, 1),
  75. #if defined(CONFIG_TARGET_P1020RDB_PD)
  76. /* 2G DDR on P1020MBG, map the second 1G */
  77. SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
  78. CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
  79. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  80. 0, 9, BOOKE_PAGESZ_1G, 1),
  81. #endif
  82. #endif /* RAMBOOT/SPL */
  83. #ifdef CONFIG_SYS_INIT_L2_ADDR
  84. /* *I*G - L2SRAM */
  85. SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
  86. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
  87. 0, 11, BOOKE_PAGESZ_256K, 1),
  88. #if CONFIG_SYS_L2_SIZE >= (256 << 10)
  89. SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
  90. CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
  91. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  92. 0, 12, BOOKE_PAGESZ_256K, 1)
  93. #endif
  94. #endif
  95. };
  96. int num_tlb_entries = ARRAY_SIZE(tlb_table);