init.c 1.3 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Configuration for MediaTek MT8518 SoC
  4. *
  5. * Copyright (C) 2019 MediaTek Inc.
  6. * Author: Mingming Lee <mingming.lee@mediatek.com>
  7. */
  8. #include <clk.h>
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <dm.h>
  12. #include <fdtdec.h>
  13. #include <init.h>
  14. #include <ram.h>
  15. #include <asm/arch/misc.h>
  16. #include <asm/armv8/mmu.h>
  17. #include <asm/cache.h>
  18. #include <asm/sections.h>
  19. #include <dm/uclass.h>
  20. #include <dt-bindings/clock/mt8518-clk.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. int dram_init(void)
  23. {
  24. int ret;
  25. ret = fdtdec_setup_memory_banksize();
  26. if (ret)
  27. return ret;
  28. return fdtdec_setup_mem_size_base();
  29. }
  30. int dram_init_banksize(void)
  31. {
  32. gd->bd->bi_dram[0].start = gd->ram_base;
  33. gd->bd->bi_dram[0].size = gd->ram_size;
  34. return 0;
  35. }
  36. void reset_cpu(ulong addr)
  37. {
  38. psci_system_reset();
  39. }
  40. int print_cpuinfo(void)
  41. {
  42. printf("CPU: MediaTek MT8518\n");
  43. return 0;
  44. }
  45. static struct mm_region mt8518_mem_map[] = {
  46. {
  47. /* DDR */
  48. .virt = 0x40000000UL,
  49. .phys = 0x40000000UL,
  50. .size = 0x20000000UL,
  51. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
  52. }, {
  53. .virt = 0x00000000UL,
  54. .phys = 0x00000000UL,
  55. .size = 0x20000000UL,
  56. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  57. PTE_BLOCK_NON_SHARE |
  58. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  59. }, {
  60. 0,
  61. }
  62. };
  63. struct mm_region *mem_map = mt8518_mem_map;