Kconfig 33 KB

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  1. menu "mpc85xx CPU"
  2. depends on MPC85xx
  3. config SYS_CPU
  4. default "mpc85xx"
  5. config CMD_ERRATA
  6. bool "Enable the 'errata' command"
  7. depends on MPC85xx
  8. default y
  9. help
  10. This enables the 'errata' command which displays a list of errata
  11. work-arounds which are enabled for the current board.
  12. choice
  13. prompt "Target select"
  14. optional
  15. config TARGET_SBC8548
  16. bool "Support sbc8548"
  17. select ARCH_MPC8548
  18. config TARGET_SOCRATES
  19. bool "Support socrates"
  20. select ARCH_MPC8544
  21. config TARGET_B4420QDS
  22. bool "Support B4420QDS"
  23. select ARCH_B4420
  24. select SUPPORT_SPL
  25. select PHYS_64BIT
  26. imply PANIC_HANG
  27. config TARGET_B4860QDS
  28. bool "Support B4860QDS"
  29. select ARCH_B4860
  30. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  31. select SUPPORT_SPL
  32. select PHYS_64BIT
  33. imply PANIC_HANG
  34. config TARGET_BSC9131RDB
  35. bool "Support BSC9131RDB"
  36. select ARCH_BSC9131
  37. select SUPPORT_SPL
  38. select BOARD_EARLY_INIT_F
  39. config TARGET_BSC9132QDS
  40. bool "Support BSC9132QDS"
  41. select ARCH_BSC9132
  42. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  43. select SUPPORT_SPL
  44. select BOARD_EARLY_INIT_F
  45. config TARGET_C29XPCIE
  46. bool "Support C29XPCIE"
  47. select ARCH_C29X
  48. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  49. select SUPPORT_SPL
  50. select SUPPORT_TPL
  51. select PHYS_64BIT
  52. imply PANIC_HANG
  53. config TARGET_P3041DS
  54. bool "Support P3041DS"
  55. select PHYS_64BIT
  56. select ARCH_P3041
  57. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  58. imply CMD_SATA
  59. imply PANIC_HANG
  60. config TARGET_P4080DS
  61. bool "Support P4080DS"
  62. select PHYS_64BIT
  63. select ARCH_P4080
  64. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  65. imply CMD_SATA
  66. imply PANIC_HANG
  67. config TARGET_P5020DS
  68. bool "Support P5020DS"
  69. select PHYS_64BIT
  70. select ARCH_P5020
  71. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  72. imply CMD_SATA
  73. imply PANIC_HANG
  74. config TARGET_P5040DS
  75. bool "Support P5040DS"
  76. select PHYS_64BIT
  77. select ARCH_P5040
  78. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  79. imply CMD_SATA
  80. imply PANIC_HANG
  81. config TARGET_MPC8536DS
  82. bool "Support MPC8536DS"
  83. select ARCH_MPC8536
  84. # Use DDR3 controller with DDR2 DIMMs on this board
  85. select SYS_FSL_DDRC_GEN3
  86. imply CMD_SATA
  87. imply FSL_SATA
  88. config TARGET_MPC8541CDS
  89. bool "Support MPC8541CDS"
  90. select ARCH_MPC8541
  91. config TARGET_MPC8544DS
  92. bool "Support MPC8544DS"
  93. select ARCH_MPC8544
  94. imply PANIC_HANG
  95. config TARGET_MPC8548CDS
  96. bool "Support MPC8548CDS"
  97. select ARCH_MPC8548
  98. config TARGET_MPC8555CDS
  99. bool "Support MPC8555CDS"
  100. select ARCH_MPC8555
  101. config TARGET_MPC8568MDS
  102. bool "Support MPC8568MDS"
  103. select ARCH_MPC8568
  104. config TARGET_MPC8569MDS
  105. bool "Support MPC8569MDS"
  106. select ARCH_MPC8569
  107. config TARGET_MPC8572DS
  108. bool "Support MPC8572DS"
  109. select ARCH_MPC8572
  110. # Use DDR3 controller with DDR2 DIMMs on this board
  111. select SYS_FSL_DDRC_GEN3
  112. imply SCSI
  113. imply PANIC_HANG
  114. config TARGET_P1010RDB_PA
  115. bool "Support P1010RDB_PA"
  116. select ARCH_P1010
  117. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  118. select SUPPORT_SPL
  119. select SUPPORT_TPL
  120. imply CMD_EEPROM
  121. imply CMD_SATA
  122. imply PANIC_HANG
  123. config TARGET_P1010RDB_PB
  124. bool "Support P1010RDB_PB"
  125. select ARCH_P1010
  126. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  127. select SUPPORT_SPL
  128. select SUPPORT_TPL
  129. imply CMD_EEPROM
  130. imply CMD_SATA
  131. imply PANIC_HANG
  132. config TARGET_P1022DS
  133. bool "Support P1022DS"
  134. select ARCH_P1022
  135. select SUPPORT_SPL
  136. select SUPPORT_TPL
  137. imply CMD_SATA
  138. imply FSL_SATA
  139. config TARGET_P1023RDB
  140. bool "Support P1023RDB"
  141. select ARCH_P1023
  142. imply CMD_EEPROM
  143. imply PANIC_HANG
  144. config TARGET_P1020MBG
  145. bool "Support P1020MBG-PC"
  146. select SUPPORT_SPL
  147. select SUPPORT_TPL
  148. select ARCH_P1020
  149. imply CMD_EEPROM
  150. imply CMD_SATA
  151. imply PANIC_HANG
  152. config TARGET_P1020RDB_PC
  153. bool "Support P1020RDB-PC"
  154. select SUPPORT_SPL
  155. select SUPPORT_TPL
  156. select ARCH_P1020
  157. imply CMD_EEPROM
  158. imply CMD_SATA
  159. imply PANIC_HANG
  160. config TARGET_P1020RDB_PD
  161. bool "Support P1020RDB-PD"
  162. select SUPPORT_SPL
  163. select SUPPORT_TPL
  164. select ARCH_P1020
  165. imply CMD_EEPROM
  166. imply CMD_SATA
  167. imply PANIC_HANG
  168. config TARGET_P1020UTM
  169. bool "Support P1020UTM"
  170. select SUPPORT_SPL
  171. select SUPPORT_TPL
  172. select ARCH_P1020
  173. imply CMD_EEPROM
  174. imply CMD_SATA
  175. imply PANIC_HANG
  176. config TARGET_P1021RDB
  177. bool "Support P1021RDB"
  178. select SUPPORT_SPL
  179. select SUPPORT_TPL
  180. select ARCH_P1021
  181. imply CMD_EEPROM
  182. imply CMD_SATA
  183. imply PANIC_HANG
  184. config TARGET_P1024RDB
  185. bool "Support P1024RDB"
  186. select SUPPORT_SPL
  187. select SUPPORT_TPL
  188. select ARCH_P1024
  189. imply CMD_EEPROM
  190. imply CMD_SATA
  191. imply PANIC_HANG
  192. config TARGET_P1025RDB
  193. bool "Support P1025RDB"
  194. select SUPPORT_SPL
  195. select SUPPORT_TPL
  196. select ARCH_P1025
  197. imply CMD_EEPROM
  198. imply CMD_SATA
  199. imply SATA_SIL
  200. config TARGET_P2020RDB
  201. bool "Support P2020RDB-PC"
  202. select SUPPORT_SPL
  203. select SUPPORT_TPL
  204. select ARCH_P2020
  205. imply CMD_EEPROM
  206. imply CMD_SATA
  207. imply SATA_SIL
  208. config TARGET_P1_TWR
  209. bool "Support p1_twr"
  210. select ARCH_P1025
  211. config TARGET_P2041RDB
  212. bool "Support P2041RDB"
  213. select ARCH_P2041
  214. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  215. select PHYS_64BIT
  216. imply CMD_SATA
  217. imply FSL_SATA
  218. config TARGET_QEMU_PPCE500
  219. bool "Support qemu-ppce500"
  220. select ARCH_QEMU_E500
  221. select PHYS_64BIT
  222. config TARGET_T1024QDS
  223. bool "Support T1024QDS"
  224. select ARCH_T1024
  225. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  226. select SUPPORT_SPL
  227. select PHYS_64BIT
  228. imply CMD_EEPROM
  229. imply CMD_SATA
  230. imply FSL_SATA
  231. config TARGET_T1023RDB
  232. bool "Support T1023RDB"
  233. select ARCH_T1023
  234. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  235. select SUPPORT_SPL
  236. select PHYS_64BIT
  237. imply CMD_EEPROM
  238. imply PANIC_HANG
  239. config TARGET_T1024RDB
  240. bool "Support T1024RDB"
  241. select ARCH_T1024
  242. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  243. select SUPPORT_SPL
  244. select PHYS_64BIT
  245. imply CMD_EEPROM
  246. imply PANIC_HANG
  247. config TARGET_T1040QDS
  248. bool "Support T1040QDS"
  249. select ARCH_T1040
  250. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  251. select PHYS_64BIT
  252. imply CMD_EEPROM
  253. imply CMD_SATA
  254. imply PANIC_HANG
  255. config TARGET_T1040RDB
  256. bool "Support T1040RDB"
  257. select ARCH_T1040
  258. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  259. select SUPPORT_SPL
  260. select PHYS_64BIT
  261. imply CMD_SATA
  262. imply PANIC_HANG
  263. config TARGET_T1040D4RDB
  264. bool "Support T1040D4RDB"
  265. select ARCH_T1040
  266. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  267. select SUPPORT_SPL
  268. select PHYS_64BIT
  269. imply CMD_SATA
  270. imply PANIC_HANG
  271. config TARGET_T1042RDB
  272. bool "Support T1042RDB"
  273. select ARCH_T1042
  274. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  275. select SUPPORT_SPL
  276. select PHYS_64BIT
  277. imply CMD_SATA
  278. config TARGET_T1042D4RDB
  279. bool "Support T1042D4RDB"
  280. select ARCH_T1042
  281. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  282. select SUPPORT_SPL
  283. select PHYS_64BIT
  284. imply CMD_SATA
  285. imply PANIC_HANG
  286. config TARGET_T1042RDB_PI
  287. bool "Support T1042RDB_PI"
  288. select ARCH_T1042
  289. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  290. select SUPPORT_SPL
  291. select PHYS_64BIT
  292. imply CMD_SATA
  293. imply PANIC_HANG
  294. config TARGET_T2080QDS
  295. bool "Support T2080QDS"
  296. select ARCH_T2080
  297. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  298. select SUPPORT_SPL
  299. select PHYS_64BIT
  300. imply CMD_SATA
  301. config TARGET_T2080RDB
  302. bool "Support T2080RDB"
  303. select ARCH_T2080
  304. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  305. select SUPPORT_SPL
  306. select PHYS_64BIT
  307. imply CMD_SATA
  308. imply PANIC_HANG
  309. config TARGET_T2081QDS
  310. bool "Support T2081QDS"
  311. select ARCH_T2081
  312. select SUPPORT_SPL
  313. select PHYS_64BIT
  314. config TARGET_T4160QDS
  315. bool "Support T4160QDS"
  316. select ARCH_T4160
  317. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  318. select SUPPORT_SPL
  319. select PHYS_64BIT
  320. imply CMD_SATA
  321. imply PANIC_HANG
  322. config TARGET_T4160RDB
  323. bool "Support T4160RDB"
  324. select ARCH_T4160
  325. select SUPPORT_SPL
  326. select PHYS_64BIT
  327. imply PANIC_HANG
  328. config TARGET_T4240QDS
  329. bool "Support T4240QDS"
  330. select ARCH_T4240
  331. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  332. select SUPPORT_SPL
  333. select PHYS_64BIT
  334. imply CMD_SATA
  335. imply PANIC_HANG
  336. config TARGET_T4240RDB
  337. bool "Support T4240RDB"
  338. select ARCH_T4240
  339. select SUPPORT_SPL
  340. select PHYS_64BIT
  341. imply CMD_SATA
  342. imply PANIC_HANG
  343. config TARGET_CONTROLCENTERD
  344. bool "Support controlcenterd"
  345. select ARCH_P1022
  346. config TARGET_KMP204X
  347. bool "Support kmp204x"
  348. select ARCH_P2041
  349. select PHYS_64BIT
  350. imply CMD_CRAMFS
  351. imply FS_CRAMFS
  352. config TARGET_XPEDITE520X
  353. bool "Support xpedite520x"
  354. select ARCH_MPC8548
  355. config TARGET_XPEDITE537X
  356. bool "Support xpedite537x"
  357. select ARCH_MPC8572
  358. # Use DDR3 controller with DDR2 DIMMs on this board
  359. select SYS_FSL_DDRC_GEN3
  360. config TARGET_XPEDITE550X
  361. bool "Support xpedite550x"
  362. select ARCH_P2020
  363. config TARGET_UCP1020
  364. bool "Support uCP1020"
  365. select ARCH_P1020
  366. imply CMD_SATA
  367. imply PANIC_HANG
  368. config TARGET_CYRUS_P5020
  369. bool "Support Varisys Cyrus P5020"
  370. select ARCH_P5020
  371. select PHYS_64BIT
  372. imply PANIC_HANG
  373. config TARGET_CYRUS_P5040
  374. bool "Support Varisys Cyrus P5040"
  375. select ARCH_P5040
  376. select PHYS_64BIT
  377. imply PANIC_HANG
  378. endchoice
  379. config ARCH_B4420
  380. bool
  381. select E500MC
  382. select E6500
  383. select FSL_LAW
  384. select SYS_FSL_DDR_VER_47
  385. select SYS_FSL_ERRATUM_A004477
  386. select SYS_FSL_ERRATUM_A005871
  387. select SYS_FSL_ERRATUM_A006379
  388. select SYS_FSL_ERRATUM_A006384
  389. select SYS_FSL_ERRATUM_A006475
  390. select SYS_FSL_ERRATUM_A006593
  391. select SYS_FSL_ERRATUM_A007075
  392. select SYS_FSL_ERRATUM_A007186
  393. select SYS_FSL_ERRATUM_A007212
  394. select SYS_FSL_ERRATUM_A009942
  395. select SYS_FSL_HAS_DDR3
  396. select SYS_FSL_HAS_SEC
  397. select SYS_FSL_QORIQ_CHASSIS2
  398. select SYS_FSL_SEC_BE
  399. select SYS_FSL_SEC_COMPAT_4
  400. select SYS_PPC64
  401. select FSL_IFC
  402. imply CMD_EEPROM
  403. imply CMD_NAND
  404. imply CMD_REGINFO
  405. config ARCH_B4860
  406. bool
  407. select E500MC
  408. select E6500
  409. select FSL_LAW
  410. select SYS_FSL_DDR_VER_47
  411. select SYS_FSL_ERRATUM_A004477
  412. select SYS_FSL_ERRATUM_A005871
  413. select SYS_FSL_ERRATUM_A006379
  414. select SYS_FSL_ERRATUM_A006384
  415. select SYS_FSL_ERRATUM_A006475
  416. select SYS_FSL_ERRATUM_A006593
  417. select SYS_FSL_ERRATUM_A007075
  418. select SYS_FSL_ERRATUM_A007186
  419. select SYS_FSL_ERRATUM_A007212
  420. select SYS_FSL_ERRATUM_A007907
  421. select SYS_FSL_ERRATUM_A009942
  422. select SYS_FSL_HAS_DDR3
  423. select SYS_FSL_HAS_SEC
  424. select SYS_FSL_QORIQ_CHASSIS2
  425. select SYS_FSL_SEC_BE
  426. select SYS_FSL_SEC_COMPAT_4
  427. select SYS_PPC64
  428. select FSL_IFC
  429. imply CMD_EEPROM
  430. imply CMD_NAND
  431. imply CMD_REGINFO
  432. config ARCH_BSC9131
  433. bool
  434. select FSL_LAW
  435. select SYS_FSL_DDR_VER_44
  436. select SYS_FSL_ERRATUM_A004477
  437. select SYS_FSL_ERRATUM_A005125
  438. select SYS_FSL_ERRATUM_ESDHC111
  439. select SYS_FSL_HAS_DDR3
  440. select SYS_FSL_HAS_SEC
  441. select SYS_FSL_SEC_BE
  442. select SYS_FSL_SEC_COMPAT_4
  443. select FSL_IFC
  444. imply CMD_EEPROM
  445. imply CMD_NAND
  446. imply CMD_REGINFO
  447. config ARCH_BSC9132
  448. bool
  449. select FSL_LAW
  450. select SYS_FSL_DDR_VER_46
  451. select SYS_FSL_ERRATUM_A004477
  452. select SYS_FSL_ERRATUM_A005125
  453. select SYS_FSL_ERRATUM_A005434
  454. select SYS_FSL_ERRATUM_ESDHC111
  455. select SYS_FSL_ERRATUM_I2C_A004447
  456. select SYS_FSL_ERRATUM_IFC_A002769
  457. select SYS_FSL_HAS_DDR3
  458. select SYS_FSL_HAS_SEC
  459. select SYS_FSL_SEC_BE
  460. select SYS_FSL_SEC_COMPAT_4
  461. select SYS_PPC_E500_USE_DEBUG_TLB
  462. select FSL_IFC
  463. imply CMD_EEPROM
  464. imply CMD_MTDPARTS
  465. imply CMD_NAND
  466. imply CMD_PCI
  467. imply CMD_REGINFO
  468. config ARCH_C29X
  469. bool
  470. select FSL_LAW
  471. select SYS_FSL_DDR_VER_46
  472. select SYS_FSL_ERRATUM_A005125
  473. select SYS_FSL_ERRATUM_ESDHC111
  474. select SYS_FSL_HAS_DDR3
  475. select SYS_FSL_HAS_SEC
  476. select SYS_FSL_SEC_BE
  477. select SYS_FSL_SEC_COMPAT_6
  478. select SYS_PPC_E500_USE_DEBUG_TLB
  479. select FSL_IFC
  480. imply CMD_NAND
  481. imply CMD_PCI
  482. imply CMD_REGINFO
  483. config ARCH_MPC8536
  484. bool
  485. select FSL_LAW
  486. select SYS_FSL_ERRATUM_A004508
  487. select SYS_FSL_ERRATUM_A005125
  488. select SYS_FSL_HAS_DDR2
  489. select SYS_FSL_HAS_DDR3
  490. select SYS_FSL_HAS_SEC
  491. select SYS_FSL_SEC_BE
  492. select SYS_FSL_SEC_COMPAT_2
  493. select SYS_PPC_E500_USE_DEBUG_TLB
  494. select FSL_ELBC
  495. imply CMD_NAND
  496. imply CMD_SATA
  497. imply CMD_REGINFO
  498. config ARCH_MPC8540
  499. bool
  500. select FSL_LAW
  501. select SYS_FSL_HAS_DDR1
  502. config ARCH_MPC8541
  503. bool
  504. select FSL_LAW
  505. select SYS_FSL_HAS_DDR1
  506. select SYS_FSL_HAS_SEC
  507. select SYS_FSL_SEC_BE
  508. select SYS_FSL_SEC_COMPAT_2
  509. config ARCH_MPC8544
  510. bool
  511. select FSL_LAW
  512. select SYS_FSL_ERRATUM_A005125
  513. select SYS_FSL_HAS_DDR2
  514. select SYS_FSL_HAS_SEC
  515. select SYS_FSL_SEC_BE
  516. select SYS_FSL_SEC_COMPAT_2
  517. select SYS_PPC_E500_USE_DEBUG_TLB
  518. select FSL_ELBC
  519. config ARCH_MPC8548
  520. bool
  521. select FSL_LAW
  522. select SYS_FSL_ERRATUM_A005125
  523. select SYS_FSL_ERRATUM_NMG_DDR120
  524. select SYS_FSL_ERRATUM_NMG_LBC103
  525. select SYS_FSL_ERRATUM_NMG_ETSEC129
  526. select SYS_FSL_ERRATUM_I2C_A004447
  527. select SYS_FSL_HAS_DDR2
  528. select SYS_FSL_HAS_DDR1
  529. select SYS_FSL_HAS_SEC
  530. select SYS_FSL_SEC_BE
  531. select SYS_FSL_SEC_COMPAT_2
  532. select SYS_PPC_E500_USE_DEBUG_TLB
  533. imply CMD_REGINFO
  534. config ARCH_MPC8555
  535. bool
  536. select FSL_LAW
  537. select SYS_FSL_HAS_DDR1
  538. select SYS_FSL_HAS_SEC
  539. select SYS_FSL_SEC_BE
  540. select SYS_FSL_SEC_COMPAT_2
  541. config ARCH_MPC8560
  542. bool
  543. select FSL_LAW
  544. select SYS_FSL_HAS_DDR1
  545. config ARCH_MPC8568
  546. bool
  547. select FSL_LAW
  548. select SYS_FSL_HAS_DDR2
  549. select SYS_FSL_HAS_SEC
  550. select SYS_FSL_SEC_BE
  551. select SYS_FSL_SEC_COMPAT_2
  552. config ARCH_MPC8569
  553. bool
  554. select FSL_LAW
  555. select SYS_FSL_ERRATUM_A004508
  556. select SYS_FSL_ERRATUM_A005125
  557. select SYS_FSL_HAS_DDR3
  558. select SYS_FSL_HAS_SEC
  559. select SYS_FSL_SEC_BE
  560. select SYS_FSL_SEC_COMPAT_2
  561. select FSL_ELBC
  562. imply CMD_NAND
  563. config ARCH_MPC8572
  564. bool
  565. select FSL_LAW
  566. select SYS_FSL_ERRATUM_A004508
  567. select SYS_FSL_ERRATUM_A005125
  568. select SYS_FSL_ERRATUM_DDR_115
  569. select SYS_FSL_ERRATUM_DDR111_DDR134
  570. select SYS_FSL_HAS_DDR2
  571. select SYS_FSL_HAS_DDR3
  572. select SYS_FSL_HAS_SEC
  573. select SYS_FSL_SEC_BE
  574. select SYS_FSL_SEC_COMPAT_2
  575. select SYS_PPC_E500_USE_DEBUG_TLB
  576. select FSL_ELBC
  577. imply CMD_NAND
  578. config ARCH_P1010
  579. bool
  580. select FSL_LAW
  581. select SYS_FSL_ERRATUM_A004477
  582. select SYS_FSL_ERRATUM_A004508
  583. select SYS_FSL_ERRATUM_A005125
  584. select SYS_FSL_ERRATUM_A005275
  585. select SYS_FSL_ERRATUM_A006261
  586. select SYS_FSL_ERRATUM_A007075
  587. select SYS_FSL_ERRATUM_ESDHC111
  588. select SYS_FSL_ERRATUM_I2C_A004447
  589. select SYS_FSL_ERRATUM_IFC_A002769
  590. select SYS_FSL_ERRATUM_P1010_A003549
  591. select SYS_FSL_ERRATUM_SEC_A003571
  592. select SYS_FSL_ERRATUM_IFC_A003399
  593. select SYS_FSL_HAS_DDR3
  594. select SYS_FSL_HAS_SEC
  595. select SYS_FSL_SEC_BE
  596. select SYS_FSL_SEC_COMPAT_4
  597. select SYS_PPC_E500_USE_DEBUG_TLB
  598. select FSL_IFC
  599. imply CMD_EEPROM
  600. imply CMD_MTDPARTS
  601. imply CMD_NAND
  602. imply CMD_SATA
  603. imply CMD_PCI
  604. imply CMD_REGINFO
  605. imply FSL_SATA
  606. config ARCH_P1011
  607. bool
  608. select FSL_LAW
  609. select SYS_FSL_ERRATUM_A004508
  610. select SYS_FSL_ERRATUM_A005125
  611. select SYS_FSL_ERRATUM_ELBC_A001
  612. select SYS_FSL_ERRATUM_ESDHC111
  613. select SYS_FSL_HAS_DDR3
  614. select SYS_FSL_HAS_SEC
  615. select SYS_FSL_SEC_BE
  616. select SYS_FSL_SEC_COMPAT_2
  617. select SYS_PPC_E500_USE_DEBUG_TLB
  618. select FSL_ELBC
  619. config ARCH_P1020
  620. bool
  621. select FSL_LAW
  622. select SYS_FSL_ERRATUM_A004508
  623. select SYS_FSL_ERRATUM_A005125
  624. select SYS_FSL_ERRATUM_ELBC_A001
  625. select SYS_FSL_ERRATUM_ESDHC111
  626. select SYS_FSL_HAS_DDR3
  627. select SYS_FSL_HAS_SEC
  628. select SYS_FSL_SEC_BE
  629. select SYS_FSL_SEC_COMPAT_2
  630. select SYS_PPC_E500_USE_DEBUG_TLB
  631. select FSL_ELBC
  632. imply CMD_NAND
  633. imply CMD_SATA
  634. imply CMD_PCI
  635. imply CMD_REGINFO
  636. imply SATA_SIL
  637. config ARCH_P1021
  638. bool
  639. select FSL_LAW
  640. select SYS_FSL_ERRATUM_A004508
  641. select SYS_FSL_ERRATUM_A005125
  642. select SYS_FSL_ERRATUM_ELBC_A001
  643. select SYS_FSL_ERRATUM_ESDHC111
  644. select SYS_FSL_HAS_DDR3
  645. select SYS_FSL_HAS_SEC
  646. select SYS_FSL_SEC_BE
  647. select SYS_FSL_SEC_COMPAT_2
  648. select SYS_PPC_E500_USE_DEBUG_TLB
  649. select FSL_ELBC
  650. imply CMD_REGINFO
  651. imply CMD_NAND
  652. imply CMD_SATA
  653. imply CMD_REGINFO
  654. imply SATA_SIL
  655. config ARCH_P1022
  656. bool
  657. select FSL_LAW
  658. select SYS_FSL_ERRATUM_A004477
  659. select SYS_FSL_ERRATUM_A004508
  660. select SYS_FSL_ERRATUM_A005125
  661. select SYS_FSL_ERRATUM_ELBC_A001
  662. select SYS_FSL_ERRATUM_ESDHC111
  663. select SYS_FSL_ERRATUM_SATA_A001
  664. select SYS_FSL_HAS_DDR3
  665. select SYS_FSL_HAS_SEC
  666. select SYS_FSL_SEC_BE
  667. select SYS_FSL_SEC_COMPAT_2
  668. select SYS_PPC_E500_USE_DEBUG_TLB
  669. select FSL_ELBC
  670. config ARCH_P1023
  671. bool
  672. select FSL_LAW
  673. select SYS_FSL_ERRATUM_A004508
  674. select SYS_FSL_ERRATUM_A005125
  675. select SYS_FSL_ERRATUM_I2C_A004447
  676. select SYS_FSL_HAS_DDR3
  677. select SYS_FSL_HAS_SEC
  678. select SYS_FSL_SEC_BE
  679. select SYS_FSL_SEC_COMPAT_4
  680. select FSL_ELBC
  681. config ARCH_P1024
  682. bool
  683. select FSL_LAW
  684. select SYS_FSL_ERRATUM_A004508
  685. select SYS_FSL_ERRATUM_A005125
  686. select SYS_FSL_ERRATUM_ELBC_A001
  687. select SYS_FSL_ERRATUM_ESDHC111
  688. select SYS_FSL_HAS_DDR3
  689. select SYS_FSL_HAS_SEC
  690. select SYS_FSL_SEC_BE
  691. select SYS_FSL_SEC_COMPAT_2
  692. select SYS_PPC_E500_USE_DEBUG_TLB
  693. select FSL_ELBC
  694. imply CMD_EEPROM
  695. imply CMD_NAND
  696. imply CMD_SATA
  697. imply CMD_PCI
  698. imply CMD_REGINFO
  699. imply SATA_SIL
  700. config ARCH_P1025
  701. bool
  702. select FSL_LAW
  703. select SYS_FSL_ERRATUM_A004508
  704. select SYS_FSL_ERRATUM_A005125
  705. select SYS_FSL_ERRATUM_ELBC_A001
  706. select SYS_FSL_ERRATUM_ESDHC111
  707. select SYS_FSL_HAS_DDR3
  708. select SYS_FSL_HAS_SEC
  709. select SYS_FSL_SEC_BE
  710. select SYS_FSL_SEC_COMPAT_2
  711. select SYS_PPC_E500_USE_DEBUG_TLB
  712. select FSL_ELBC
  713. imply CMD_SATA
  714. imply CMD_REGINFO
  715. config ARCH_P2020
  716. bool
  717. select FSL_LAW
  718. select SYS_FSL_ERRATUM_A004477
  719. select SYS_FSL_ERRATUM_A004508
  720. select SYS_FSL_ERRATUM_A005125
  721. select SYS_FSL_ERRATUM_ESDHC111
  722. select SYS_FSL_ERRATUM_ESDHC_A001
  723. select SYS_FSL_HAS_DDR3
  724. select SYS_FSL_HAS_SEC
  725. select SYS_FSL_SEC_BE
  726. select SYS_FSL_SEC_COMPAT_2
  727. select SYS_PPC_E500_USE_DEBUG_TLB
  728. select FSL_ELBC
  729. imply CMD_EEPROM
  730. imply CMD_NAND
  731. imply CMD_REGINFO
  732. config ARCH_P2041
  733. bool
  734. select E500MC
  735. select FSL_LAW
  736. select SYS_FSL_ERRATUM_A004510
  737. select SYS_FSL_ERRATUM_A004849
  738. select SYS_FSL_ERRATUM_A005275
  739. select SYS_FSL_ERRATUM_A006261
  740. select SYS_FSL_ERRATUM_CPU_A003999
  741. select SYS_FSL_ERRATUM_DDR_A003
  742. select SYS_FSL_ERRATUM_DDR_A003474
  743. select SYS_FSL_ERRATUM_ESDHC111
  744. select SYS_FSL_ERRATUM_I2C_A004447
  745. select SYS_FSL_ERRATUM_NMG_CPU_A011
  746. select SYS_FSL_ERRATUM_SRIO_A004034
  747. select SYS_FSL_ERRATUM_USB14
  748. select SYS_FSL_HAS_DDR3
  749. select SYS_FSL_HAS_SEC
  750. select SYS_FSL_QORIQ_CHASSIS1
  751. select SYS_FSL_SEC_BE
  752. select SYS_FSL_SEC_COMPAT_4
  753. select FSL_ELBC
  754. imply CMD_NAND
  755. config ARCH_P3041
  756. bool
  757. select E500MC
  758. select FSL_LAW
  759. select SYS_FSL_DDR_VER_44
  760. select SYS_FSL_ERRATUM_A004510
  761. select SYS_FSL_ERRATUM_A004849
  762. select SYS_FSL_ERRATUM_A005275
  763. select SYS_FSL_ERRATUM_A005812
  764. select SYS_FSL_ERRATUM_A006261
  765. select SYS_FSL_ERRATUM_CPU_A003999
  766. select SYS_FSL_ERRATUM_DDR_A003
  767. select SYS_FSL_ERRATUM_DDR_A003474
  768. select SYS_FSL_ERRATUM_ESDHC111
  769. select SYS_FSL_ERRATUM_I2C_A004447
  770. select SYS_FSL_ERRATUM_NMG_CPU_A011
  771. select SYS_FSL_ERRATUM_SRIO_A004034
  772. select SYS_FSL_ERRATUM_USB14
  773. select SYS_FSL_HAS_DDR3
  774. select SYS_FSL_HAS_SEC
  775. select SYS_FSL_QORIQ_CHASSIS1
  776. select SYS_FSL_SEC_BE
  777. select SYS_FSL_SEC_COMPAT_4
  778. select FSL_ELBC
  779. imply CMD_NAND
  780. imply CMD_SATA
  781. imply CMD_REGINFO
  782. imply FSL_SATA
  783. config ARCH_P4080
  784. bool
  785. select E500MC
  786. select FSL_LAW
  787. select SYS_FSL_DDR_VER_44
  788. select SYS_FSL_ERRATUM_A004510
  789. select SYS_FSL_ERRATUM_A004580
  790. select SYS_FSL_ERRATUM_A004849
  791. select SYS_FSL_ERRATUM_A005812
  792. select SYS_FSL_ERRATUM_A007075
  793. select SYS_FSL_ERRATUM_CPC_A002
  794. select SYS_FSL_ERRATUM_CPC_A003
  795. select SYS_FSL_ERRATUM_CPU_A003999
  796. select SYS_FSL_ERRATUM_DDR_A003
  797. select SYS_FSL_ERRATUM_DDR_A003474
  798. select SYS_FSL_ERRATUM_ELBC_A001
  799. select SYS_FSL_ERRATUM_ESDHC111
  800. select SYS_FSL_ERRATUM_ESDHC13
  801. select SYS_FSL_ERRATUM_ESDHC135
  802. select SYS_FSL_ERRATUM_I2C_A004447
  803. select SYS_FSL_ERRATUM_NMG_CPU_A011
  804. select SYS_FSL_ERRATUM_SRIO_A004034
  805. select SYS_P4080_ERRATUM_CPU22
  806. select SYS_P4080_ERRATUM_PCIE_A003
  807. select SYS_P4080_ERRATUM_SERDES8
  808. select SYS_P4080_ERRATUM_SERDES9
  809. select SYS_P4080_ERRATUM_SERDES_A001
  810. select SYS_P4080_ERRATUM_SERDES_A005
  811. select SYS_FSL_HAS_DDR3
  812. select SYS_FSL_HAS_SEC
  813. select SYS_FSL_QORIQ_CHASSIS1
  814. select SYS_FSL_SEC_BE
  815. select SYS_FSL_SEC_COMPAT_4
  816. select FSL_ELBC
  817. imply CMD_SATA
  818. imply CMD_REGINFO
  819. imply SATA_SIL
  820. config ARCH_P5020
  821. bool
  822. select E500MC
  823. select FSL_LAW
  824. select SYS_FSL_DDR_VER_44
  825. select SYS_FSL_ERRATUM_A004510
  826. select SYS_FSL_ERRATUM_A005275
  827. select SYS_FSL_ERRATUM_A006261
  828. select SYS_FSL_ERRATUM_DDR_A003
  829. select SYS_FSL_ERRATUM_DDR_A003474
  830. select SYS_FSL_ERRATUM_ESDHC111
  831. select SYS_FSL_ERRATUM_I2C_A004447
  832. select SYS_FSL_ERRATUM_SRIO_A004034
  833. select SYS_FSL_ERRATUM_USB14
  834. select SYS_FSL_HAS_DDR3
  835. select SYS_FSL_HAS_SEC
  836. select SYS_FSL_QORIQ_CHASSIS1
  837. select SYS_FSL_SEC_BE
  838. select SYS_FSL_SEC_COMPAT_4
  839. select SYS_PPC64
  840. select FSL_ELBC
  841. imply CMD_SATA
  842. imply CMD_REGINFO
  843. imply FSL_SATA
  844. config ARCH_P5040
  845. bool
  846. select E500MC
  847. select FSL_LAW
  848. select SYS_FSL_DDR_VER_44
  849. select SYS_FSL_ERRATUM_A004510
  850. select SYS_FSL_ERRATUM_A004699
  851. select SYS_FSL_ERRATUM_A005275
  852. select SYS_FSL_ERRATUM_A005812
  853. select SYS_FSL_ERRATUM_A006261
  854. select SYS_FSL_ERRATUM_DDR_A003
  855. select SYS_FSL_ERRATUM_DDR_A003474
  856. select SYS_FSL_ERRATUM_ESDHC111
  857. select SYS_FSL_ERRATUM_USB14
  858. select SYS_FSL_HAS_DDR3
  859. select SYS_FSL_HAS_SEC
  860. select SYS_FSL_QORIQ_CHASSIS1
  861. select SYS_FSL_SEC_BE
  862. select SYS_FSL_SEC_COMPAT_4
  863. select SYS_PPC64
  864. select FSL_ELBC
  865. imply CMD_SATA
  866. imply CMD_REGINFO
  867. imply FSL_SATA
  868. config ARCH_QEMU_E500
  869. bool
  870. config ARCH_T1023
  871. bool
  872. select E500MC
  873. select FSL_LAW
  874. select SYS_FSL_DDR_VER_50
  875. select SYS_FSL_ERRATUM_A008378
  876. select SYS_FSL_ERRATUM_A009663
  877. select SYS_FSL_ERRATUM_A009942
  878. select SYS_FSL_ERRATUM_ESDHC111
  879. select SYS_FSL_HAS_DDR3
  880. select SYS_FSL_HAS_DDR4
  881. select SYS_FSL_HAS_SEC
  882. select SYS_FSL_QORIQ_CHASSIS2
  883. select SYS_FSL_SEC_BE
  884. select SYS_FSL_SEC_COMPAT_5
  885. select FSL_IFC
  886. imply CMD_EEPROM
  887. imply CMD_NAND
  888. imply CMD_REGINFO
  889. config ARCH_T1024
  890. bool
  891. select E500MC
  892. select FSL_LAW
  893. select SYS_FSL_DDR_VER_50
  894. select SYS_FSL_ERRATUM_A008378
  895. select SYS_FSL_ERRATUM_A009663
  896. select SYS_FSL_ERRATUM_A009942
  897. select SYS_FSL_ERRATUM_ESDHC111
  898. select SYS_FSL_HAS_DDR3
  899. select SYS_FSL_HAS_DDR4
  900. select SYS_FSL_HAS_SEC
  901. select SYS_FSL_QORIQ_CHASSIS2
  902. select SYS_FSL_SEC_BE
  903. select SYS_FSL_SEC_COMPAT_5
  904. select FSL_IFC
  905. imply CMD_EEPROM
  906. imply CMD_NAND
  907. imply CMD_MTDPARTS
  908. imply CMD_REGINFO
  909. config ARCH_T1040
  910. bool
  911. select E500MC
  912. select FSL_LAW
  913. select SYS_FSL_DDR_VER_50
  914. select SYS_FSL_ERRATUM_A008044
  915. select SYS_FSL_ERRATUM_A008378
  916. select SYS_FSL_ERRATUM_A009663
  917. select SYS_FSL_ERRATUM_A009942
  918. select SYS_FSL_ERRATUM_ESDHC111
  919. select SYS_FSL_HAS_DDR3
  920. select SYS_FSL_HAS_DDR4
  921. select SYS_FSL_HAS_SEC
  922. select SYS_FSL_QORIQ_CHASSIS2
  923. select SYS_FSL_SEC_BE
  924. select SYS_FSL_SEC_COMPAT_5
  925. select FSL_IFC
  926. imply CMD_MTDPARTS
  927. imply CMD_NAND
  928. imply CMD_SATA
  929. imply CMD_REGINFO
  930. imply FSL_SATA
  931. config ARCH_T1042
  932. bool
  933. select E500MC
  934. select FSL_LAW
  935. select SYS_FSL_DDR_VER_50
  936. select SYS_FSL_ERRATUM_A008044
  937. select SYS_FSL_ERRATUM_A008378
  938. select SYS_FSL_ERRATUM_A009663
  939. select SYS_FSL_ERRATUM_A009942
  940. select SYS_FSL_ERRATUM_ESDHC111
  941. select SYS_FSL_HAS_DDR3
  942. select SYS_FSL_HAS_DDR4
  943. select SYS_FSL_HAS_SEC
  944. select SYS_FSL_QORIQ_CHASSIS2
  945. select SYS_FSL_SEC_BE
  946. select SYS_FSL_SEC_COMPAT_5
  947. select FSL_IFC
  948. imply CMD_MTDPARTS
  949. imply CMD_NAND
  950. imply CMD_SATA
  951. imply CMD_REGINFO
  952. imply FSL_SATA
  953. config ARCH_T2080
  954. bool
  955. select E500MC
  956. select E6500
  957. select FSL_LAW
  958. select SYS_FSL_DDR_VER_47
  959. select SYS_FSL_ERRATUM_A006379
  960. select SYS_FSL_ERRATUM_A006593
  961. select SYS_FSL_ERRATUM_A007186
  962. select SYS_FSL_ERRATUM_A007212
  963. select SYS_FSL_ERRATUM_A007815
  964. select SYS_FSL_ERRATUM_A007907
  965. select SYS_FSL_ERRATUM_A009942
  966. select SYS_FSL_ERRATUM_ESDHC111
  967. select SYS_FSL_HAS_DDR3
  968. select SYS_FSL_HAS_SEC
  969. select SYS_FSL_QORIQ_CHASSIS2
  970. select SYS_FSL_SEC_BE
  971. select SYS_FSL_SEC_COMPAT_4
  972. select SYS_PPC64
  973. select FSL_IFC
  974. imply CMD_SATA
  975. imply CMD_NAND
  976. imply CMD_REGINFO
  977. imply FSL_SATA
  978. config ARCH_T2081
  979. bool
  980. select E500MC
  981. select E6500
  982. select FSL_LAW
  983. select SYS_FSL_DDR_VER_47
  984. select SYS_FSL_ERRATUM_A006379
  985. select SYS_FSL_ERRATUM_A006593
  986. select SYS_FSL_ERRATUM_A007186
  987. select SYS_FSL_ERRATUM_A007212
  988. select SYS_FSL_ERRATUM_A009942
  989. select SYS_FSL_ERRATUM_ESDHC111
  990. select SYS_FSL_HAS_DDR3
  991. select SYS_FSL_HAS_SEC
  992. select SYS_FSL_QORIQ_CHASSIS2
  993. select SYS_FSL_SEC_BE
  994. select SYS_FSL_SEC_COMPAT_4
  995. select SYS_PPC64
  996. select FSL_IFC
  997. imply CMD_NAND
  998. imply CMD_REGINFO
  999. config ARCH_T4160
  1000. bool
  1001. select E500MC
  1002. select E6500
  1003. select FSL_LAW
  1004. select SYS_FSL_DDR_VER_47
  1005. select SYS_FSL_ERRATUM_A004468
  1006. select SYS_FSL_ERRATUM_A005871
  1007. select SYS_FSL_ERRATUM_A006379
  1008. select SYS_FSL_ERRATUM_A006593
  1009. select SYS_FSL_ERRATUM_A007186
  1010. select SYS_FSL_ERRATUM_A007798
  1011. select SYS_FSL_ERRATUM_A009942
  1012. select SYS_FSL_HAS_DDR3
  1013. select SYS_FSL_HAS_SEC
  1014. select SYS_FSL_QORIQ_CHASSIS2
  1015. select SYS_FSL_SEC_BE
  1016. select SYS_FSL_SEC_COMPAT_4
  1017. select SYS_PPC64
  1018. select FSL_IFC
  1019. imply CMD_SATA
  1020. imply CMD_NAND
  1021. imply CMD_REGINFO
  1022. imply FSL_SATA
  1023. config ARCH_T4240
  1024. bool
  1025. select E500MC
  1026. select E6500
  1027. select FSL_LAW
  1028. select SYS_FSL_DDR_VER_47
  1029. select SYS_FSL_ERRATUM_A004468
  1030. select SYS_FSL_ERRATUM_A005871
  1031. select SYS_FSL_ERRATUM_A006261
  1032. select SYS_FSL_ERRATUM_A006379
  1033. select SYS_FSL_ERRATUM_A006593
  1034. select SYS_FSL_ERRATUM_A007186
  1035. select SYS_FSL_ERRATUM_A007798
  1036. select SYS_FSL_ERRATUM_A007815
  1037. select SYS_FSL_ERRATUM_A007907
  1038. select SYS_FSL_ERRATUM_A009942
  1039. select SYS_FSL_HAS_DDR3
  1040. select SYS_FSL_HAS_SEC
  1041. select SYS_FSL_QORIQ_CHASSIS2
  1042. select SYS_FSL_SEC_BE
  1043. select SYS_FSL_SEC_COMPAT_4
  1044. select SYS_PPC64
  1045. select FSL_IFC
  1046. imply CMD_SATA
  1047. imply CMD_NAND
  1048. imply CMD_REGINFO
  1049. imply FSL_SATA
  1050. config MPC85XX_HAVE_RESET_VECTOR
  1051. bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
  1052. depends on MPC85xx
  1053. config BOOKE
  1054. bool
  1055. default y
  1056. config E500
  1057. bool
  1058. default y
  1059. help
  1060. Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
  1061. config E500MC
  1062. bool
  1063. imply CMD_PCI
  1064. help
  1065. Enble PowerPC E500MC core
  1066. config E6500
  1067. bool
  1068. help
  1069. Enable PowerPC E6500 core
  1070. config FSL_LAW
  1071. bool
  1072. help
  1073. Use Freescale common code for Local Access Window
  1074. config SECURE_BOOT
  1075. bool "Secure Boot"
  1076. help
  1077. Enable Freescale Secure Boot feature. Normally selected
  1078. by defconfig. If unsure, do not change.
  1079. config MAX_CPUS
  1080. int "Maximum number of CPUs permitted for MPC85xx"
  1081. default 12 if ARCH_T4240
  1082. default 8 if ARCH_P4080 || \
  1083. ARCH_T4160
  1084. default 4 if ARCH_B4860 || \
  1085. ARCH_P2041 || \
  1086. ARCH_P3041 || \
  1087. ARCH_P5040 || \
  1088. ARCH_T1040 || \
  1089. ARCH_T1042 || \
  1090. ARCH_T2080 || \
  1091. ARCH_T2081
  1092. default 2 if ARCH_B4420 || \
  1093. ARCH_BSC9132 || \
  1094. ARCH_MPC8572 || \
  1095. ARCH_P1020 || \
  1096. ARCH_P1021 || \
  1097. ARCH_P1022 || \
  1098. ARCH_P1023 || \
  1099. ARCH_P1024 || \
  1100. ARCH_P1025 || \
  1101. ARCH_P2020 || \
  1102. ARCH_P5020 || \
  1103. ARCH_T1023 || \
  1104. ARCH_T1024
  1105. default 1
  1106. help
  1107. Set this number to the maximum number of possible CPUs in the SoC.
  1108. SoCs may have multiple clusters with each cluster may have multiple
  1109. ports. If some ports are reserved but higher ports are used for
  1110. cores, count the reserved ports. This will allocate enough memory
  1111. in spin table to properly handle all cores.
  1112. config SYS_CCSRBAR_DEFAULT
  1113. hex "Default CCSRBAR address"
  1114. default 0xff700000 if ARCH_BSC9131 || \
  1115. ARCH_BSC9132 || \
  1116. ARCH_C29X || \
  1117. ARCH_MPC8536 || \
  1118. ARCH_MPC8540 || \
  1119. ARCH_MPC8541 || \
  1120. ARCH_MPC8544 || \
  1121. ARCH_MPC8548 || \
  1122. ARCH_MPC8555 || \
  1123. ARCH_MPC8560 || \
  1124. ARCH_MPC8568 || \
  1125. ARCH_MPC8569 || \
  1126. ARCH_MPC8572 || \
  1127. ARCH_P1010 || \
  1128. ARCH_P1011 || \
  1129. ARCH_P1020 || \
  1130. ARCH_P1021 || \
  1131. ARCH_P1022 || \
  1132. ARCH_P1024 || \
  1133. ARCH_P1025 || \
  1134. ARCH_P2020
  1135. default 0xff600000 if ARCH_P1023
  1136. default 0xfe000000 if ARCH_B4420 || \
  1137. ARCH_B4860 || \
  1138. ARCH_P2041 || \
  1139. ARCH_P3041 || \
  1140. ARCH_P4080 || \
  1141. ARCH_P5020 || \
  1142. ARCH_P5040 || \
  1143. ARCH_T1023 || \
  1144. ARCH_T1024 || \
  1145. ARCH_T1040 || \
  1146. ARCH_T1042 || \
  1147. ARCH_T2080 || \
  1148. ARCH_T2081 || \
  1149. ARCH_T4160 || \
  1150. ARCH_T4240
  1151. default 0xe0000000 if ARCH_QEMU_E500
  1152. help
  1153. Default value of CCSRBAR comes from power-on-reset. It
  1154. is fixed on each SoC. Some SoCs can have different value
  1155. if changed by pre-boot regime. The value here must match
  1156. the current value in SoC. If not sure, do not change.
  1157. config SYS_FSL_ERRATUM_A004468
  1158. bool
  1159. config SYS_FSL_ERRATUM_A004477
  1160. bool
  1161. config SYS_FSL_ERRATUM_A004508
  1162. bool
  1163. config SYS_FSL_ERRATUM_A004580
  1164. bool
  1165. config SYS_FSL_ERRATUM_A004699
  1166. bool
  1167. config SYS_FSL_ERRATUM_A004849
  1168. bool
  1169. config SYS_FSL_ERRATUM_A004510
  1170. bool
  1171. config SYS_FSL_ERRATUM_A004510_SVR_REV
  1172. hex
  1173. depends on SYS_FSL_ERRATUM_A004510
  1174. default 0x20 if ARCH_P4080
  1175. default 0x10
  1176. config SYS_FSL_ERRATUM_A004510_SVR_REV2
  1177. hex
  1178. depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
  1179. default 0x11
  1180. config SYS_FSL_ERRATUM_A005125
  1181. bool
  1182. config SYS_FSL_ERRATUM_A005434
  1183. bool
  1184. config SYS_FSL_ERRATUM_A005812
  1185. bool
  1186. config SYS_FSL_ERRATUM_A005871
  1187. bool
  1188. config SYS_FSL_ERRATUM_A005275
  1189. bool
  1190. config SYS_FSL_ERRATUM_A006261
  1191. bool
  1192. config SYS_FSL_ERRATUM_A006379
  1193. bool
  1194. config SYS_FSL_ERRATUM_A006384
  1195. bool
  1196. config SYS_FSL_ERRATUM_A006475
  1197. bool
  1198. config SYS_FSL_ERRATUM_A006593
  1199. bool
  1200. config SYS_FSL_ERRATUM_A007075
  1201. bool
  1202. config SYS_FSL_ERRATUM_A007186
  1203. bool
  1204. config SYS_FSL_ERRATUM_A007212
  1205. bool
  1206. config SYS_FSL_ERRATUM_A007815
  1207. bool
  1208. config SYS_FSL_ERRATUM_A007798
  1209. bool
  1210. config SYS_FSL_ERRATUM_A007907
  1211. bool
  1212. config SYS_FSL_ERRATUM_A008044
  1213. bool
  1214. config SYS_FSL_ERRATUM_CPC_A002
  1215. bool
  1216. config SYS_FSL_ERRATUM_CPC_A003
  1217. bool
  1218. config SYS_FSL_ERRATUM_CPU_A003999
  1219. bool
  1220. config SYS_FSL_ERRATUM_ELBC_A001
  1221. bool
  1222. config SYS_FSL_ERRATUM_I2C_A004447
  1223. bool
  1224. config SYS_FSL_A004447_SVR_REV
  1225. hex
  1226. depends on SYS_FSL_ERRATUM_I2C_A004447
  1227. default 0x00 if ARCH_MPC8548
  1228. default 0x10 if ARCH_P1010
  1229. default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
  1230. default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
  1231. config SYS_FSL_ERRATUM_IFC_A002769
  1232. bool
  1233. config SYS_FSL_ERRATUM_IFC_A003399
  1234. bool
  1235. config SYS_FSL_ERRATUM_NMG_CPU_A011
  1236. bool
  1237. config SYS_FSL_ERRATUM_NMG_ETSEC129
  1238. bool
  1239. config SYS_FSL_ERRATUM_NMG_LBC103
  1240. bool
  1241. config SYS_FSL_ERRATUM_P1010_A003549
  1242. bool
  1243. config SYS_FSL_ERRATUM_SATA_A001
  1244. bool
  1245. config SYS_FSL_ERRATUM_SEC_A003571
  1246. bool
  1247. config SYS_FSL_ERRATUM_SRIO_A004034
  1248. bool
  1249. config SYS_FSL_ERRATUM_USB14
  1250. bool
  1251. config SYS_P4080_ERRATUM_CPU22
  1252. bool
  1253. config SYS_P4080_ERRATUM_PCIE_A003
  1254. bool
  1255. config SYS_P4080_ERRATUM_SERDES8
  1256. bool
  1257. config SYS_P4080_ERRATUM_SERDES9
  1258. bool
  1259. config SYS_P4080_ERRATUM_SERDES_A001
  1260. bool
  1261. config SYS_P4080_ERRATUM_SERDES_A005
  1262. bool
  1263. config SYS_FSL_QORIQ_CHASSIS1
  1264. bool
  1265. config SYS_FSL_QORIQ_CHASSIS2
  1266. bool
  1267. config SYS_FSL_NUM_LAWS
  1268. int "Number of local access windows"
  1269. depends on FSL_LAW
  1270. default 32 if ARCH_B4420 || \
  1271. ARCH_B4860 || \
  1272. ARCH_P2041 || \
  1273. ARCH_P3041 || \
  1274. ARCH_P4080 || \
  1275. ARCH_P5020 || \
  1276. ARCH_P5040 || \
  1277. ARCH_T2080 || \
  1278. ARCH_T2081 || \
  1279. ARCH_T4160 || \
  1280. ARCH_T4240
  1281. default 16 if ARCH_T1023 || \
  1282. ARCH_T1024 || \
  1283. ARCH_T1040 || \
  1284. ARCH_T1042
  1285. default 12 if ARCH_BSC9131 || \
  1286. ARCH_BSC9132 || \
  1287. ARCH_C29X || \
  1288. ARCH_MPC8536 || \
  1289. ARCH_MPC8572 || \
  1290. ARCH_P1010 || \
  1291. ARCH_P1011 || \
  1292. ARCH_P1020 || \
  1293. ARCH_P1021 || \
  1294. ARCH_P1022 || \
  1295. ARCH_P1023 || \
  1296. ARCH_P1024 || \
  1297. ARCH_P1025 || \
  1298. ARCH_P2020
  1299. default 10 if ARCH_MPC8544 || \
  1300. ARCH_MPC8548 || \
  1301. ARCH_MPC8568 || \
  1302. ARCH_MPC8569
  1303. default 8 if ARCH_MPC8540 || \
  1304. ARCH_MPC8541 || \
  1305. ARCH_MPC8555 || \
  1306. ARCH_MPC8560
  1307. help
  1308. Number of local access windows. This is fixed per SoC.
  1309. If not sure, do not change.
  1310. config SYS_FSL_THREADS_PER_CORE
  1311. int
  1312. default 2 if E6500
  1313. default 1
  1314. config SYS_NUM_TLBCAMS
  1315. int "Number of TLB CAM entries"
  1316. default 64 if E500MC
  1317. default 16
  1318. help
  1319. Number of TLB CAM entries for Book-E chips. 64 for E500MC,
  1320. 16 for other E500 SoCs.
  1321. config SYS_PPC64
  1322. bool
  1323. config SYS_PPC_E500_USE_DEBUG_TLB
  1324. bool
  1325. config FSL_IFC
  1326. bool
  1327. config FSL_ELBC
  1328. bool
  1329. config SYS_PPC_E500_DEBUG_TLB
  1330. int "Temporary TLB entry for external debugger"
  1331. depends on SYS_PPC_E500_USE_DEBUG_TLB
  1332. default 0 if ARCH_MPC8544 || ARCH_MPC8548
  1333. default 1 if ARCH_MPC8536
  1334. default 2 if ARCH_MPC8572 || \
  1335. ARCH_P1011 || \
  1336. ARCH_P1020 || \
  1337. ARCH_P1021 || \
  1338. ARCH_P1022 || \
  1339. ARCH_P1024 || \
  1340. ARCH_P1025 || \
  1341. ARCH_P2020
  1342. default 3 if ARCH_P1010 || \
  1343. ARCH_BSC9132 || \
  1344. ARCH_C29X
  1345. help
  1346. Select a temporary TLB entry to be used during boot to work
  1347. around limitations in e500v1 and e500v2 external debugger
  1348. support. This reduces the portions of the boot code where
  1349. breakpoints and single stepping do not work. The value of this
  1350. symbol should be set to the TLB1 entry to be used for this
  1351. purpose. If unsure, do not change.
  1352. config SYS_FSL_IFC_CLK_DIV
  1353. int "Divider of platform clock"
  1354. depends on FSL_IFC
  1355. default 2 if ARCH_B4420 || \
  1356. ARCH_B4860 || \
  1357. ARCH_T1024 || \
  1358. ARCH_T1023 || \
  1359. ARCH_T1040 || \
  1360. ARCH_T1042 || \
  1361. ARCH_T4160 || \
  1362. ARCH_T4240
  1363. default 1
  1364. help
  1365. Defines divider of platform clock(clock input to
  1366. IFC controller).
  1367. config SYS_FSL_LBC_CLK_DIV
  1368. int "Divider of platform clock"
  1369. depends on FSL_ELBC || ARCH_MPC8540 || \
  1370. ARCH_MPC8548 || ARCH_MPC8541 || \
  1371. ARCH_MPC8555 || ARCH_MPC8560 || \
  1372. ARCH_MPC8568
  1373. default 2 if ARCH_P2041 || \
  1374. ARCH_P3041 || \
  1375. ARCH_P4080 || \
  1376. ARCH_P5020 || \
  1377. ARCH_P5040
  1378. default 1
  1379. help
  1380. Defines divider of platform clock(clock input to
  1381. eLBC controller).
  1382. source "board/freescale/b4860qds/Kconfig"
  1383. source "board/freescale/bsc9131rdb/Kconfig"
  1384. source "board/freescale/bsc9132qds/Kconfig"
  1385. source "board/freescale/c29xpcie/Kconfig"
  1386. source "board/freescale/corenet_ds/Kconfig"
  1387. source "board/freescale/mpc8536ds/Kconfig"
  1388. source "board/freescale/mpc8541cds/Kconfig"
  1389. source "board/freescale/mpc8544ds/Kconfig"
  1390. source "board/freescale/mpc8548cds/Kconfig"
  1391. source "board/freescale/mpc8555cds/Kconfig"
  1392. source "board/freescale/mpc8568mds/Kconfig"
  1393. source "board/freescale/mpc8569mds/Kconfig"
  1394. source "board/freescale/mpc8572ds/Kconfig"
  1395. source "board/freescale/p1010rdb/Kconfig"
  1396. source "board/freescale/p1022ds/Kconfig"
  1397. source "board/freescale/p1023rdb/Kconfig"
  1398. source "board/freescale/p1_p2_rdb_pc/Kconfig"
  1399. source "board/freescale/p1_twr/Kconfig"
  1400. source "board/freescale/p2041rdb/Kconfig"
  1401. source "board/freescale/qemu-ppce500/Kconfig"
  1402. source "board/freescale/t102xqds/Kconfig"
  1403. source "board/freescale/t102xrdb/Kconfig"
  1404. source "board/freescale/t1040qds/Kconfig"
  1405. source "board/freescale/t104xrdb/Kconfig"
  1406. source "board/freescale/t208xqds/Kconfig"
  1407. source "board/freescale/t208xrdb/Kconfig"
  1408. source "board/freescale/t4qds/Kconfig"
  1409. source "board/freescale/t4rdb/Kconfig"
  1410. source "board/gdsys/p1022/Kconfig"
  1411. source "board/keymile/kmp204x/Kconfig"
  1412. source "board/sbc8548/Kconfig"
  1413. source "board/socrates/Kconfig"
  1414. source "board/varisys/cyrus/Kconfig"
  1415. source "board/xes/xpedite520x/Kconfig"
  1416. source "board/xes/xpedite537x/Kconfig"
  1417. source "board/xes/xpedite550x/Kconfig"
  1418. source "board/Arcturus/ucp1020/Kconfig"
  1419. endmenu