spl.c 2.9 KB

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  1. /*
  2. * Copyright 2018-2019 NXP
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <hang.h>
  9. #include <image.h>
  10. #include <spl.h>
  11. #include <asm/io.h>
  12. #include <errno.h>
  13. #include <asm/io.h>
  14. #include <asm/mach-imx/iomux-v3.h>
  15. #include <asm/arch/imx8mp_pins.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include <asm/mach-imx/boot_mode.h>
  18. #include <power/pmic.h>
  19. #include <power/pca9450.h>
  20. #include <asm/arch/clock.h>
  21. #include <asm/mach-imx/gpio.h>
  22. #include <asm/mach-imx/mxc_i2c.h>
  23. #include <fsl_esdhc.h>
  24. #include <mmc.h>
  25. #include <asm/arch/ddr.h>
  26. #include <dm/uclass.h>
  27. #include <dm/device.h>
  28. #include <dm/uclass-internal.h>
  29. #include <dm/device-internal.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. int spl_board_boot_device(enum boot_device boot_dev_spl)
  32. {
  33. return BOOT_DEVICE_BOOTROM;
  34. }
  35. void spl_dram_init(void)
  36. {
  37. ddr_init(&dram_timing);
  38. }
  39. void spl_board_init(void)
  40. {
  41. struct udevice *dev;
  42. int ret;
  43. puts("Normal Boot\n");
  44. ret = uclass_get_device_by_name(UCLASS_CLK,
  45. "clock-controller@30380000",
  46. &dev);
  47. if (ret < 0)
  48. printf("Failed to find clock node. Check device tree\n");
  49. }
  50. #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
  51. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  52. struct i2c_pads_info i2c_pad_info1 = {
  53. .scl = {
  54. .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
  55. .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
  56. .gp = IMX_GPIO_NR(5, 14),
  57. },
  58. .sda = {
  59. .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
  60. .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
  61. .gp = IMX_GPIO_NR(5, 15),
  62. },
  63. };
  64. #ifdef CONFIG_POWER
  65. #define I2C_PMIC 0
  66. int power_init_board(void)
  67. {
  68. struct pmic *p;
  69. int ret;
  70. ret = power_pca9450b_init(I2C_PMIC);
  71. if (ret)
  72. printf("power init failed");
  73. p = pmic_get("PCA9450");
  74. pmic_probe(p);
  75. /* BUCKxOUT_DVS0/1 control BUCK123 output */
  76. pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
  77. /*
  78. * increase VDD_SOC to typical value 0.95V before first
  79. * DRAM access, set DVS1 to 0.85v for suspend.
  80. * Enable DVS control through PMIC_STBY_REQ and
  81. * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
  82. */
  83. pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
  84. pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
  85. pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
  86. /* set WDOG_B_CFG to cold reset */
  87. pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
  88. return 0;
  89. }
  90. #endif
  91. #ifdef CONFIG_SPL_LOAD_FIT
  92. int board_fit_config_name_match(const char *name)
  93. {
  94. /* Just empty function now - can't decide what to choose */
  95. debug("%s: %s\n", __func__, name);
  96. return 0;
  97. }
  98. #endif
  99. void board_init_f(ulong dummy)
  100. {
  101. int ret;
  102. arch_cpu_init();
  103. init_uart_clk(1);
  104. board_early_init_f();
  105. timer_init();
  106. preloader_console_init();
  107. /* Clear the BSS. */
  108. memset(__bss_start, 0, __bss_end - __bss_start);
  109. ret = spl_init();
  110. if (ret) {
  111. debug("spl_init() failed: %d\n", ret);
  112. hang();
  113. }
  114. enable_tzc380();
  115. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  116. power_init_board();
  117. /* DDR initialization */
  118. spl_dram_init();
  119. board_init_r(NULL, 0);
  120. }