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- /*
- * Copyright 2018-2019 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
- #include <common.h>
- #include <cpu_func.h>
- #include <hang.h>
- #include <image.h>
- #include <spl.h>
- #include <asm/io.h>
- #include <errno.h>
- #include <asm/io.h>
- #include <asm/mach-imx/iomux-v3.h>
- #include <asm/arch/imx8mp_pins.h>
- #include <asm/arch/sys_proto.h>
- #include <asm/mach-imx/boot_mode.h>
- #include <power/pmic.h>
- #include <power/pca9450.h>
- #include <asm/arch/clock.h>
- #include <asm/mach-imx/gpio.h>
- #include <asm/mach-imx/mxc_i2c.h>
- #include <fsl_esdhc.h>
- #include <mmc.h>
- #include <asm/arch/ddr.h>
- #include <dm/uclass.h>
- #include <dm/device.h>
- #include <dm/uclass-internal.h>
- #include <dm/device-internal.h>
- DECLARE_GLOBAL_DATA_PTR;
- int spl_board_boot_device(enum boot_device boot_dev_spl)
- {
- return BOOT_DEVICE_BOOTROM;
- }
- void spl_dram_init(void)
- {
- ddr_init(&dram_timing);
- }
- void spl_board_init(void)
- {
- struct udevice *dev;
- int ret;
- puts("Normal Boot\n");
- ret = uclass_get_device_by_name(UCLASS_CLK,
- "clock-controller@30380000",
- &dev);
- if (ret < 0)
- printf("Failed to find clock node. Check device tree\n");
- }
- #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
- #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
- struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
- .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
- .gp = IMX_GPIO_NR(5, 14),
- },
- .sda = {
- .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
- .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
- .gp = IMX_GPIO_NR(5, 15),
- },
- };
- #ifdef CONFIG_POWER
- #define I2C_PMIC 0
- int power_init_board(void)
- {
- struct pmic *p;
- int ret;
- ret = power_pca9450b_init(I2C_PMIC);
- if (ret)
- printf("power init failed");
- p = pmic_get("PCA9450");
- pmic_probe(p);
- /* BUCKxOUT_DVS0/1 control BUCK123 output */
- pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
- /*
- * increase VDD_SOC to typical value 0.95V before first
- * DRAM access, set DVS1 to 0.85v for suspend.
- * Enable DVS control through PMIC_STBY_REQ and
- * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
- */
- pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
- pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
- pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
- /* set WDOG_B_CFG to cold reset */
- pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
- return 0;
- }
- #endif
- #ifdef CONFIG_SPL_LOAD_FIT
- int board_fit_config_name_match(const char *name)
- {
- /* Just empty function now - can't decide what to choose */
- debug("%s: %s\n", __func__, name);
- return 0;
- }
- #endif
- void board_init_f(ulong dummy)
- {
- int ret;
- arch_cpu_init();
- init_uart_clk(1);
- board_early_init_f();
- timer_init();
- preloader_console_init();
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
- ret = spl_init();
- if (ret) {
- debug("spl_init() failed: %d\n", ret);
- hang();
- }
- enable_tzc380();
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- power_init_board();
- /* DDR initialization */
- spl_dram_init();
- board_init_r(NULL, 0);
- }
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