spl.c 2.2 KB

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  1. /*
  2. * Copyright 2018-2019 NXP
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <hang.h>
  9. #include <image.h>
  10. #include <spl.h>
  11. #include <asm/io.h>
  12. #include <asm/mach-imx/iomux-v3.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/imx8mn_pins.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/mach-imx/boot_mode.h>
  17. #include <asm/arch/ddr.h>
  18. #include <dm/uclass.h>
  19. #include <dm/device.h>
  20. #include <dm/uclass-internal.h>
  21. #include <dm/device-internal.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. int spl_board_boot_device(enum boot_device boot_dev_spl)
  24. {
  25. return BOOT_DEVICE_BOOTROM;
  26. }
  27. void spl_dram_init(void)
  28. {
  29. ddr_init(&dram_timing);
  30. }
  31. void spl_board_init(void)
  32. {
  33. struct udevice *dev;
  34. int ret;
  35. puts("Normal Boot\n");
  36. ret = uclass_get_device_by_name(UCLASS_CLK,
  37. "clock-controller@30380000",
  38. &dev);
  39. if (ret < 0)
  40. printf("Failed to find clock node. Check device tree\n");
  41. }
  42. #ifdef CONFIG_SPL_LOAD_FIT
  43. int board_fit_config_name_match(const char *name)
  44. {
  45. /* Just empty function now - can't decide what to choose */
  46. debug("%s: %s\n", __func__, name);
  47. return 0;
  48. }
  49. #endif
  50. #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  51. #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  52. static iomux_v3_cfg_t const uart_pads[] = {
  53. IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  54. IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  55. };
  56. static iomux_v3_cfg_t const wdog_pads[] = {
  57. IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  58. };
  59. int board_early_init_f(void)
  60. {
  61. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  62. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  63. set_wdog_reset(wdog);
  64. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  65. init_uart_clk(1);
  66. return 0;
  67. }
  68. void board_init_f(ulong dummy)
  69. {
  70. int ret;
  71. arch_cpu_init();
  72. init_uart_clk(1);
  73. board_early_init_f();
  74. timer_init();
  75. preloader_console_init();
  76. /* Clear the BSS. */
  77. memset(__bss_start, 0, __bss_end - __bss_start);
  78. ret = spl_init();
  79. if (ret) {
  80. debug("spl_init() failed: %d\n", ret);
  81. hang();
  82. }
  83. enable_tzc380();
  84. /* DDR initialization */
  85. spl_dram_init();
  86. board_init_r(NULL, 0);
  87. }