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@@ -9,6 +9,7 @@
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* Haikun Wang (B53464@freescale.com)
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*/
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+#include <linux/math64.h>
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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@@ -25,6 +26,9 @@
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#include <linux/bitops.h>
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#include <linux/delay.h>
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+/* linux/include/time.h */
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+#define NSEC_PER_SEC 1000000000L
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+
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DECLARE_GLOBAL_DATA_PTR;
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/* fsl_dspi_platdata flags */
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@@ -379,6 +383,40 @@ static int fsl_dspi_hz_to_spi_baud(int *pbr, int *br,
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return -EINVAL;
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}
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+static void ns_delay_scale(unsigned char *psc, unsigned char *sc, int delay_ns,
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+ unsigned long clkrate)
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+{
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+ int scale_needed, scale, minscale = INT_MAX;
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+ int pscale_tbl[4] = {1, 3, 5, 7};
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+ u32 remainder;
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+ int i, j;
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+
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+ scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
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+ &remainder);
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+ if (remainder)
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+ scale_needed++;
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+
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+ for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
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+ for (j = 0; j <= DSPI_CTAR_SCALE_BITS; j++) {
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+ scale = pscale_tbl[i] * (2 << j);
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+ if (scale >= scale_needed) {
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+ if (scale < minscale) {
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+ minscale = scale;
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+ *psc = i;
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+ *sc = j;
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+ }
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+ break;
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+ }
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+ }
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+
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+ if (minscale == INT_MAX) {
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+ pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
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+ delay_ns, clkrate);
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+ *psc = ARRAY_SIZE(pscale_tbl) - 1;
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+ *sc = DSPI_CTAR_SCALE_BITS;
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+ }
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+}
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+
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static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed)
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{
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int ret;
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@@ -412,6 +450,9 @@ static int fsl_dspi_child_pre_probe(struct udevice *dev)
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{
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struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
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struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
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+ u32 cs_sck_delay = 0, sck_cs_delay = 0;
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+ unsigned char pcssck = 0, cssck = 0;
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+ unsigned char pasc = 0, asc = 0;
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if (slave_plat->cs >= priv->num_chipselect) {
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debug("DSPI invalid chipselect number %d(max %d)!\n",
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@@ -419,7 +460,18 @@ static int fsl_dspi_child_pre_probe(struct udevice *dev)
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return -EINVAL;
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}
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- priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE;
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+ ofnode_read_u32(dev->node, "fsl,spi-cs-sck-delay", &cs_sck_delay);
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+ ofnode_read_u32(dev->node, "fsl,spi-sck-cs-delay", &sck_cs_delay);
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+
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+ /* Set PCS to SCK delay scale values */
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+ ns_delay_scale(&pcssck, &cssck, cs_sck_delay, priv->bus_clk);
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+
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+ /* Set After SCK delay scale values */
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+ ns_delay_scale(&pasc, &asc, sck_cs_delay, priv->bus_clk);
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+
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+ priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE |
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+ DSPI_CTAR_PCSSCK(pcssck) |
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+ DSPI_CTAR_PASC(pasc);
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debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n",
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slave_plat->cs, slave_plat->max_hz, slave_plat->mode);
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