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@@ -1,36 +1,37 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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+ * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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+ * Copyright (C) 2018, Anup Patel <anup@brainfault.org>
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+ * Copyright (C) 2012 Regents of the University of California
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*
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- * RISC-V privileged architecture defined generic timer driver
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+ * RISC-V architecturally-defined generic timer driver
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*
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- * This driver relies on RISC-V platform codes to provide the essential API
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- * riscv_get_time() which is supposed to return the timer counter as defined
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- * by the RISC-V privileged architecture spec.
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- *
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- * This driver can be used in both M-mode and S-mode U-Boot.
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+ * This driver provides generic timer support for S-mode U-Boot.
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <timer.h>
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-#include <asm/io.h>
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-
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-/**
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- * riscv_get_time() - get the timer counter
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- *
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- * Platform codes should provide this API in order to make this driver function.
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- *
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- * @time: the 64-bit timer count as defined by the RISC-V privileged
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- * architecture spec.
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- * @return: 0 on success, -ve on error.
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- */
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-extern int riscv_get_time(u64 *time);
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+#include <asm/csr.h>
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static int riscv_timer_get_count(struct udevice *dev, u64 *count)
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{
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- return riscv_get_time(count);
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+ if (IS_ENABLED(CONFIG_64BIT)) {
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+ *count = csr_read(CSR_TIME);
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+ } else {
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+ u32 hi, lo;
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+
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+ do {
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+ hi = csr_read(CSR_TIMEH);
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+ lo = csr_read(CSR_TIME);
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+ } while (hi != csr_read(CSR_TIMEH));
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+
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+ *count = ((u64)hi << 32) | lo;
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+ }
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+
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+ return 0;
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}
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static int riscv_timer_probe(struct udevice *dev)
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