Kconfig 6.5 KB

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  1. menu "RISC-V architecture"
  2. depends on RISCV
  3. config SYS_ARCH
  4. default "riscv"
  5. choice
  6. prompt "Target select"
  7. optional
  8. config TARGET_AX25_AE350
  9. bool "Support ax25-ae350"
  10. config TARGET_MICROCHIP_ICICLE
  11. bool "Support Microchip PolarFire-SoC Icicle Board"
  12. config TARGET_QEMU_VIRT
  13. bool "Support QEMU Virt Board"
  14. config TARGET_SIFIVE_FU540
  15. bool "Support SiFive FU540 Board"
  16. config TARGET_SIPEED_MAIX
  17. bool "Support Sipeed Maix Board"
  18. endchoice
  19. config SYS_ICACHE_OFF
  20. bool "Do not enable icache"
  21. default n
  22. help
  23. Do not enable instruction cache in U-Boot.
  24. config SPL_SYS_ICACHE_OFF
  25. bool "Do not enable icache in SPL"
  26. depends on SPL
  27. default SYS_ICACHE_OFF
  28. help
  29. Do not enable instruction cache in SPL.
  30. config SYS_DCACHE_OFF
  31. bool "Do not enable dcache"
  32. default n
  33. help
  34. Do not enable data cache in U-Boot.
  35. config SPL_SYS_DCACHE_OFF
  36. bool "Do not enable dcache in SPL"
  37. depends on SPL
  38. default SYS_DCACHE_OFF
  39. help
  40. Do not enable data cache in SPL.
  41. # board-specific options below
  42. source "board/AndesTech/ax25-ae350/Kconfig"
  43. source "board/emulation/qemu-riscv/Kconfig"
  44. source "board/microchip/mpfs_icicle/Kconfig"
  45. source "board/sifive/fu540/Kconfig"
  46. source "board/sipeed/maix/Kconfig"
  47. # platform-specific options below
  48. source "arch/riscv/cpu/ax25/Kconfig"
  49. source "arch/riscv/cpu/fu540/Kconfig"
  50. source "arch/riscv/cpu/generic/Kconfig"
  51. # architecture-specific options below
  52. choice
  53. prompt "Base ISA"
  54. default ARCH_RV32I
  55. config ARCH_RV32I
  56. bool "RV32I"
  57. select 32BIT
  58. help
  59. Choose this option to target the RV32I base integer instruction set.
  60. config ARCH_RV64I
  61. bool "RV64I"
  62. select 64BIT
  63. select PHYS_64BIT
  64. help
  65. Choose this option to target the RV64I base integer instruction set.
  66. endchoice
  67. choice
  68. prompt "Code Model"
  69. default CMODEL_MEDLOW
  70. config CMODEL_MEDLOW
  71. bool "medium low code model"
  72. help
  73. U-Boot and its statically defined symbols must lie within a single 2 GiB
  74. address range and must lie between absolute addresses -2 GiB and +2 GiB.
  75. config CMODEL_MEDANY
  76. bool "medium any code model"
  77. help
  78. U-Boot and its statically defined symbols must be within any single 2 GiB
  79. address range.
  80. endchoice
  81. choice
  82. prompt "Run Mode"
  83. default RISCV_MMODE
  84. config RISCV_MMODE
  85. bool "Machine"
  86. help
  87. Choose this option to build U-Boot for RISC-V M-Mode.
  88. config RISCV_SMODE
  89. bool "Supervisor"
  90. help
  91. Choose this option to build U-Boot for RISC-V S-Mode.
  92. endchoice
  93. choice
  94. prompt "SPL Run Mode"
  95. default SPL_RISCV_MMODE
  96. depends on SPL
  97. config SPL_RISCV_MMODE
  98. bool "Machine"
  99. help
  100. Choose this option to build U-Boot SPL for RISC-V M-Mode.
  101. config SPL_RISCV_SMODE
  102. bool "Supervisor"
  103. help
  104. Choose this option to build U-Boot SPL for RISC-V S-Mode.
  105. endchoice
  106. config RISCV_ISA_C
  107. bool "Emit compressed instructions"
  108. default y
  109. help
  110. Adds "C" to the ISA subsets that the toolchain is allowed to emit
  111. when building U-Boot, which results in compressed instructions in the
  112. U-Boot binary.
  113. config RISCV_ISA_A
  114. def_bool y
  115. config 32BIT
  116. bool
  117. config 64BIT
  118. bool
  119. config SIFIVE_CLINT
  120. bool
  121. depends on RISCV_MMODE || SPL_RISCV_MMODE
  122. select REGMAP
  123. select SYSCON
  124. select SPL_REGMAP if SPL
  125. select SPL_SYSCON if SPL
  126. help
  127. The SiFive CLINT block holds memory-mapped control and status registers
  128. associated with software and timer interrupts.
  129. config ANDES_PLIC
  130. bool
  131. depends on RISCV_MMODE || SPL_RISCV_MMODE
  132. select REGMAP
  133. select SYSCON
  134. select SPL_REGMAP if SPL
  135. select SPL_SYSCON if SPL
  136. help
  137. The Andes PLIC block holds memory-mapped claim and pending registers
  138. associated with software interrupt.
  139. config ANDES_PLMT
  140. bool
  141. depends on RISCV_MMODE || SPL_RISCV_MMODE
  142. select REGMAP
  143. select SYSCON
  144. select SPL_REGMAP if SPL
  145. select SPL_SYSCON if SPL
  146. help
  147. The Andes PLMT block holds memory-mapped mtime register
  148. associated with timer tick.
  149. config SYS_MALLOC_F_LEN
  150. default 0x1000
  151. config SMP
  152. bool "Symmetric Multi-Processing"
  153. depends on SBI_V01 || !RISCV_SMODE
  154. help
  155. This enables support for systems with more than one CPU. If
  156. you say N here, U-Boot will run on single and multiprocessor
  157. machines, but will use only one CPU of a multiprocessor
  158. machine. If you say Y here, U-Boot will run on many, but not
  159. all, single processor machines.
  160. config SPL_SMP
  161. bool "Symmetric Multi-Processing in SPL"
  162. depends on SPL && SPL_RISCV_MMODE
  163. default y
  164. help
  165. This enables support for systems with more than one CPU in SPL.
  166. If you say N here, U-Boot SPL will run on single and multiprocessor
  167. machines, but will use only one CPU of a multiprocessor
  168. machine. If you say Y here, U-Boot SPL will run on many, but not
  169. all, single processor machines.
  170. config NR_CPUS
  171. int "Maximum number of CPUs (2-32)"
  172. range 2 32
  173. depends on SMP || SPL_SMP
  174. default 8
  175. help
  176. On multiprocessor machines, U-Boot sets up a stack for each CPU.
  177. Stack memory is pre-allocated. U-Boot must therefore know the
  178. maximum number of CPUs that may be present.
  179. config SBI
  180. bool
  181. default y if RISCV_SMODE || SPL_RISCV_SMODE
  182. choice
  183. prompt "SBI support"
  184. default SBI_V02
  185. config SBI_V01
  186. bool "SBI v0.1 support"
  187. depends on SBI
  188. help
  189. This config allows kernel to use SBI v0.1 APIs. This will be
  190. deprecated in future once legacy M-mode software are no longer in use.
  191. config SBI_V02
  192. bool "SBI v0.2 support"
  193. depends on SBI
  194. help
  195. This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
  196. scalable and extendable to handle future needs for RISC-V supervisor
  197. interfaces. For example, with SBI v0.2 HSM extension, only a single
  198. hart need to boot and enter operating system. The booting hart can
  199. bring up secondary harts one by one afterwards.
  200. Choose this option if OpenSBI v0.7 or above release is used together
  201. with U-Boot.
  202. endchoice
  203. config SBI_IPI
  204. bool
  205. depends on SBI
  206. default y if RISCV_SMODE || SPL_RISCV_SMODE
  207. depends on SMP
  208. config XIP
  209. bool "XIP mode"
  210. help
  211. XIP (eXecute In Place) is a method for executing code directly
  212. from a NOR flash memory without copying the code to ram.
  213. Say yes here if U-Boot boots from flash directly.
  214. config SHOW_REGS
  215. bool "Show registers on unhandled exception"
  216. config RISCV_PRIV_1_9
  217. bool "Use version 1.9 of the RISC-V priviledged specification"
  218. help
  219. Older versions of the RISC-V priviledged specification had
  220. separate counter enable CSRs for each privilege mode. Writing
  221. to the unified mcounteren CSR on a processor implementing the
  222. old specification will result in an illegal instruction
  223. exception. In addition to counter CSR changes, the way virtual
  224. memory is configured was also changed.
  225. config STACK_SIZE_SHIFT
  226. int
  227. default 14
  228. config OF_BOARD_FIXUP
  229. default y if OF_SEPARATE
  230. endmenu