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@@ -34,6 +34,10 @@ void get_sys_info(sys_info_t *sys_info)
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#ifdef CONFIG_FSL_CORENET
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volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
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unsigned int cpu;
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+#ifdef CONFIG_HETROGENOUS_CLUSTERS
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+ unsigned int dsp_cpu;
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+ uint rcw_tmp1, rcw_tmp2;
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+#endif
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
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#endif
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@@ -157,6 +161,7 @@ void get_sys_info(sys_info_t *sys_info)
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else
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freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
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}
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+
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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/*
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* As per CHASSIS2 architeture total 12 clusters are posible and
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@@ -181,6 +186,20 @@ void get_sys_info(sys_info_t *sys_info)
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sys_info->freq_processor[cpu] =
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freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
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}
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+
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+#ifdef CONFIG_HETROGENOUS_CLUSTERS
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+ for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) {
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+ int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu);
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+ u32 c_pll_sel = (in_be32
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+ (&clk->clkcsr[dsp_cluster].clkcncsr) >> 27)
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+ & 0xf;
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+ u32 cplx_pll = core_cplx_PLL[c_pll_sel];
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+ cplx_pll += cc_group[dsp_cluster] - 1;
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+ sys_info->freq_processor_dsp[dsp_cpu] =
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+ freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
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+ }
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+#endif
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+
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#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
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defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
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#define FM1_CLK_SEL 0xe0000000
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@@ -243,6 +262,127 @@ void get_sys_info(sys_info_t *sys_info)
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sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
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#endif
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+#if defined(CONFIG_SYS_MAPLE)
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+#define CPRI_CLK_SEL 0x1C000000
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+#define CPRI_CLK_SHIFT 26
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+#define CPRI_ALT_CLK_SEL 0x00007000
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+#define CPRI_ALT_CLK_SHIFT 12
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+
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+ rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/
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+ rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/
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+ /* For MAPLE and CPRI frequency */
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+ switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) {
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+ case 1:
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+ sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK];
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+ sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK];
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+ break;
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+ case 2:
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+ sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
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+ sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
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+ break;
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+ case 3:
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+ sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
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+ sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
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+ break;
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+ case 4:
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+ sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
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+ sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
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+ break;
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+ case 5:
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+ if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
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+ >> CPRI_ALT_CLK_SHIFT) == 6) {
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+ sys_info->freq_maple =
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+ freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
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+ sys_info->freq_cpri =
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+ freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
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+ }
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+ if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
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+ >> CPRI_ALT_CLK_SHIFT) == 7) {
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+ sys_info->freq_maple =
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+ freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
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+ sys_info->freq_cpri =
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+ freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
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+ }
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+ break;
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+ case 6:
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+ sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
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+ sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
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+ break;
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+ case 7:
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+ sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
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+ sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
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+ break;
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+ default:
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+ printf("Error: Unknown MAPLE/CPRI clock select!\n");
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+ }
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+
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+ /* For MAPLE ULB and eTVPE frequencies */
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+#define ULB_CLK_SEL 0x00000038
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+#define ULB_CLK_SHIFT 3
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+#define ETVPE_CLK_SEL 0x00000007
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+#define ETVPE_CLK_SHIFT 0
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+
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+ switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) {
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+ case 1:
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+ sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK];
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+ break;
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+ case 2:
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+ sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2;
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+ break;
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+ case 3:
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+ sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3;
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+ break;
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+ case 4:
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+ sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4;
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+ break;
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+ case 5:
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+ sys_info->freq_maple_ulb = sys_info->freq_systembus;
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+ break;
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+ case 6:
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+ sys_info->freq_maple_ulb =
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+ freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2;
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+ break;
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+ case 7:
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+ sys_info->freq_maple_ulb =
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+ freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3;
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+ break;
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+ default:
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+ printf("Error: Unknown MAPLE ULB clock select!\n");
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+ }
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+
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+ switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) {
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+ case 1:
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+ sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK];
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+ break;
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+ case 2:
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+ sys_info->freq_maple_etvpe =
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+ freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2;
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+ break;
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+ case 3:
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+ sys_info->freq_maple_etvpe =
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+ freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3;
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+ break;
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+ case 4:
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+ sys_info->freq_maple_etvpe =
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+ freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4;
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+ break;
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+ case 5:
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+ sys_info->freq_maple_etvpe = sys_info->freq_systembus;
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+ break;
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+ case 6:
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+ sys_info->freq_maple_etvpe =
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+ freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2;
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+ break;
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+ case 7:
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+ sys_info->freq_maple_etvpe =
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+ freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3;
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+ break;
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+ default:
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+ printf("Error: Unknown MAPLE eTVPE clock select!\n");
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+ }
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+
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+#endif
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+
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#ifdef CONFIG_SYS_DPAA_FMAN
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#ifndef CONFIG_FM_PLAT_CLK_DIV
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switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
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