cpu.c 16 KB

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  1. /*
  2. * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
  3. * (C) Copyright 2002, 2003 Motorola Inc.
  4. * Xianghua Xiao (X.Xiao@motorola.com)
  5. *
  6. * (C) Copyright 2000
  7. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. */
  11. #include <config.h>
  12. #include <common.h>
  13. #include <watchdog.h>
  14. #include <command.h>
  15. #include <fsl_esdhc.h>
  16. #include <asm/cache.h>
  17. #include <asm/io.h>
  18. #include <asm/mmu.h>
  19. #include <fsl_ifc.h>
  20. #include <asm/fsl_law.h>
  21. #include <asm/fsl_lbc.h>
  22. #include <post.h>
  23. #include <asm/processor.h>
  24. #include <fsl_ddr_sdram.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. /*
  27. * Default board reset function
  28. */
  29. static void
  30. __board_reset(void)
  31. {
  32. /* Do nothing */
  33. }
  34. void board_reset(void) __attribute__((weak, alias("__board_reset")));
  35. int checkcpu (void)
  36. {
  37. sys_info_t sysinfo;
  38. uint pvr, svr;
  39. uint ver;
  40. uint major, minor;
  41. struct cpu_type *cpu;
  42. char buf1[32], buf2[32];
  43. #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
  44. ccsr_gur_t __iomem *gur =
  45. (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  46. #endif
  47. /*
  48. * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
  49. * mode. Previous platform use ddr ratio to do the same. This
  50. * information is only for display here.
  51. */
  52. #ifdef CONFIG_FSL_CORENET
  53. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  54. u32 ddr_sync = 0; /* only async mode is supported */
  55. #else
  56. u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
  57. >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
  58. #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  59. #else /* CONFIG_FSL_CORENET */
  60. #ifdef CONFIG_DDR_CLK_FREQ
  61. u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
  62. >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
  63. #else
  64. u32 ddr_ratio = 0;
  65. #endif /* CONFIG_DDR_CLK_FREQ */
  66. #endif /* CONFIG_FSL_CORENET */
  67. unsigned int i, core, nr_cores = cpu_numcores();
  68. u32 mask = cpu_mask();
  69. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  70. unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
  71. u32 dsp_mask = cpu_dsp_mask();
  72. #endif
  73. svr = get_svr();
  74. major = SVR_MAJ(svr);
  75. minor = SVR_MIN(svr);
  76. #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  77. if (SVR_SOC_VER(svr) == SVR_T4080) {
  78. ccsr_rcpm_t *rcpm =
  79. (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
  80. setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
  81. FSL_CORENET_DEVDISR2_DTSEC1_9);
  82. setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
  83. setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
  84. /* It needs SW to disable core4~7 as HW design sake on T4080 */
  85. for (i = 4; i < 8; i++)
  86. cpu_disable(i);
  87. /* request core4~7 into PH20 state, prior to entering PCL10
  88. * state, all cores in cluster should be placed in PH20 state.
  89. */
  90. setbits_be32(&rcpm->pcph20setr, 0xf0);
  91. /* put the 2nd cluster into PCL10 state */
  92. setbits_be32(&rcpm->clpcl10setr, 1 << 1);
  93. }
  94. #endif
  95. if (cpu_numcores() > 1) {
  96. #ifndef CONFIG_MP
  97. puts("Unicore software on multiprocessor system!!\n"
  98. "To enable mutlticore build define CONFIG_MP\n");
  99. #endif
  100. volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
  101. printf("CPU%d: ", pic->whoami);
  102. } else {
  103. puts("CPU: ");
  104. }
  105. cpu = gd->arch.cpu;
  106. puts(cpu->name);
  107. if (IS_E_PROCESSOR(svr))
  108. puts("E");
  109. printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  110. pvr = get_pvr();
  111. ver = PVR_VER(pvr);
  112. major = PVR_MAJ(pvr);
  113. minor = PVR_MIN(pvr);
  114. printf("Core: ");
  115. switch(ver) {
  116. case PVR_VER_E500_V1:
  117. case PVR_VER_E500_V2:
  118. puts("e500");
  119. break;
  120. case PVR_VER_E500MC:
  121. puts("e500mc");
  122. break;
  123. case PVR_VER_E5500:
  124. puts("e5500");
  125. break;
  126. case PVR_VER_E6500:
  127. puts("e6500");
  128. break;
  129. default:
  130. puts("Unknown");
  131. break;
  132. }
  133. printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
  134. if (nr_cores > CONFIG_MAX_CPUS) {
  135. panic("\nUnexpected number of cores: %d, max is %d\n",
  136. nr_cores, CONFIG_MAX_CPUS);
  137. }
  138. get_sys_info(&sysinfo);
  139. #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  140. if (sysinfo.diff_sysclk == 1)
  141. puts("Single Source Clock Configuration\n");
  142. #endif
  143. puts("Clock Configuration:");
  144. for_each_cpu(i, core, nr_cores, mask) {
  145. if (!(i & 3))
  146. printf ("\n ");
  147. printf("CPU%d:%-4s MHz, ", core,
  148. strmhz(buf1, sysinfo.freq_processor[core]));
  149. }
  150. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  151. for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
  152. if (!(j & 3))
  153. printf("\n ");
  154. printf("DSP CPU%d:%-4s MHz, ", j,
  155. strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
  156. }
  157. #endif
  158. printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
  159. printf("\n");
  160. #ifdef CONFIG_FSL_CORENET
  161. if (ddr_sync == 1) {
  162. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  163. "(Synchronous), ",
  164. strmhz(buf1, sysinfo.freq_ddrbus/2),
  165. strmhz(buf2, sysinfo.freq_ddrbus));
  166. } else {
  167. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  168. "(Asynchronous), ",
  169. strmhz(buf1, sysinfo.freq_ddrbus/2),
  170. strmhz(buf2, sysinfo.freq_ddrbus));
  171. }
  172. #else
  173. switch (ddr_ratio) {
  174. case 0x0:
  175. printf(" DDR:%-4s MHz (%s MT/s data rate), ",
  176. strmhz(buf1, sysinfo.freq_ddrbus/2),
  177. strmhz(buf2, sysinfo.freq_ddrbus));
  178. break;
  179. case 0x7:
  180. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  181. "(Synchronous), ",
  182. strmhz(buf1, sysinfo.freq_ddrbus/2),
  183. strmhz(buf2, sysinfo.freq_ddrbus));
  184. break;
  185. default:
  186. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  187. "(Asynchronous), ",
  188. strmhz(buf1, sysinfo.freq_ddrbus/2),
  189. strmhz(buf2, sysinfo.freq_ddrbus));
  190. break;
  191. }
  192. #endif
  193. #if defined(CONFIG_FSL_LBC)
  194. if (sysinfo.freq_localbus > LCRR_CLKDIV) {
  195. printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
  196. } else {
  197. printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
  198. sysinfo.freq_localbus);
  199. }
  200. #endif
  201. #if defined(CONFIG_FSL_IFC)
  202. printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
  203. #endif
  204. #ifdef CONFIG_CPM2
  205. printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
  206. #endif
  207. #ifdef CONFIG_QE
  208. printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
  209. #endif
  210. #if defined(CONFIG_SYS_CPRI)
  211. printf(" ");
  212. printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
  213. #endif
  214. #if defined(CONFIG_SYS_MAPLE)
  215. printf("\n ");
  216. printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
  217. printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
  218. printf("MAPLE-eTVPE:%-4s MHz\n",
  219. strmhz(buf1, sysinfo.freq_maple_etvpe));
  220. #endif
  221. #ifdef CONFIG_SYS_DPAA_FMAN
  222. for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
  223. printf(" FMAN%d: %s MHz\n", i + 1,
  224. strmhz(buf1, sysinfo.freq_fman[i]));
  225. }
  226. #endif
  227. #ifdef CONFIG_SYS_DPAA_QBMAN
  228. printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
  229. #endif
  230. #ifdef CONFIG_SYS_DPAA_PME
  231. printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
  232. #endif
  233. puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
  234. #ifdef CONFIG_FSL_CORENET
  235. /* Display the RCW, so that no one gets confused as to what RCW
  236. * we're actually using for this boot.
  237. */
  238. puts("Reset Configuration Word (RCW):");
  239. for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
  240. u32 rcw = in_be32(&gur->rcwsr[i]);
  241. if ((i % 4) == 0)
  242. printf("\n %08x:", i * 4);
  243. printf(" %08x", rcw);
  244. }
  245. puts("\n");
  246. #endif
  247. return 0;
  248. }
  249. /* ------------------------------------------------------------------------- */
  250. int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  251. {
  252. /* Everything after the first generation of PQ3 parts has RSTCR */
  253. #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
  254. defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
  255. unsigned long val, msr;
  256. /*
  257. * Initiate hard reset in debug control register DBCR0
  258. * Make sure MSR[DE] = 1. This only resets the core.
  259. */
  260. msr = mfmsr ();
  261. msr |= MSR_DE;
  262. mtmsr (msr);
  263. val = mfspr(DBCR0);
  264. val |= 0x70000000;
  265. mtspr(DBCR0,val);
  266. #else
  267. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  268. /* Attempt board-specific reset */
  269. board_reset();
  270. /* Next try asserting HRESET_REQ */
  271. out_be32(&gur->rstcr, 0x2);
  272. udelay(100);
  273. #endif
  274. return 1;
  275. }
  276. /*
  277. * Get timebase clock frequency
  278. */
  279. #ifndef CONFIG_SYS_FSL_TBCLK_DIV
  280. #define CONFIG_SYS_FSL_TBCLK_DIV 8
  281. #endif
  282. __weak unsigned long get_tbclk (void)
  283. {
  284. unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
  285. return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
  286. }
  287. #if defined(CONFIG_WATCHDOG)
  288. #define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
  289. void
  290. init_85xx_watchdog(void)
  291. {
  292. mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
  293. TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
  294. }
  295. void
  296. reset_85xx_watchdog(void)
  297. {
  298. /*
  299. * Clear TSR(WIS) bit by writing 1
  300. */
  301. mtspr(SPRN_TSR, TSR_WIS);
  302. }
  303. void
  304. watchdog_reset(void)
  305. {
  306. int re_enable = disable_interrupts();
  307. reset_85xx_watchdog();
  308. if (re_enable)
  309. enable_interrupts();
  310. }
  311. #endif /* CONFIG_WATCHDOG */
  312. /*
  313. * Initializes on-chip MMC controllers.
  314. * to override, implement board_mmc_init()
  315. */
  316. int cpu_mmc_init(bd_t *bis)
  317. {
  318. #ifdef CONFIG_FSL_ESDHC
  319. return fsl_esdhc_mmc_init(bis);
  320. #else
  321. return 0;
  322. #endif
  323. }
  324. /*
  325. * Print out the state of various machine registers.
  326. * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
  327. * parameters for IFC and TLBs
  328. */
  329. void mpc85xx_reginfo(void)
  330. {
  331. print_tlbcam();
  332. print_laws();
  333. #if defined(CONFIG_FSL_LBC)
  334. print_lbc_regs();
  335. #endif
  336. #ifdef CONFIG_FSL_IFC
  337. print_ifc_regs();
  338. #endif
  339. }
  340. /* Common ddr init for non-corenet fsl 85xx platforms */
  341. #ifndef CONFIG_FSL_CORENET
  342. #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
  343. !defined(CONFIG_SYS_INIT_L2_ADDR)
  344. phys_size_t initdram(int board_type)
  345. {
  346. #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
  347. defined(CONFIG_QEMU_E500)
  348. return fsl_ddr_sdram_size();
  349. #else
  350. return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  351. #endif
  352. }
  353. #else /* CONFIG_SYS_RAMBOOT */
  354. phys_size_t initdram(int board_type)
  355. {
  356. phys_size_t dram_size = 0;
  357. #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
  358. {
  359. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  360. unsigned int x = 10;
  361. unsigned int i;
  362. /*
  363. * Work around to stabilize DDR DLL
  364. */
  365. out_be32(&gur->ddrdllcr, 0x81000000);
  366. asm("sync;isync;msync");
  367. udelay(200);
  368. while (in_be32(&gur->ddrdllcr) != 0x81000100) {
  369. setbits_be32(&gur->devdisr, 0x00010000);
  370. for (i = 0; i < x; i++)
  371. ;
  372. clrbits_be32(&gur->devdisr, 0x00010000);
  373. x++;
  374. }
  375. }
  376. #endif
  377. #if defined(CONFIG_SPD_EEPROM) || \
  378. defined(CONFIG_DDR_SPD) || \
  379. defined(CONFIG_SYS_DDR_RAW_TIMING)
  380. dram_size = fsl_ddr_sdram();
  381. #else
  382. dram_size = fixed_sdram();
  383. #endif
  384. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  385. dram_size *= 0x100000;
  386. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  387. /*
  388. * Initialize and enable DDR ECC.
  389. */
  390. ddr_enable_ecc(dram_size);
  391. #endif
  392. #if defined(CONFIG_FSL_LBC)
  393. /* Some boards also have sdram on the lbc */
  394. lbc_sdram_init();
  395. #endif
  396. debug("DDR: ");
  397. return dram_size;
  398. }
  399. #endif /* CONFIG_SYS_RAMBOOT */
  400. #endif
  401. #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
  402. /* Board-specific functions defined in each board's ddr.c */
  403. void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  404. unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
  405. void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
  406. phys_addr_t *rpn);
  407. unsigned int
  408. setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
  409. void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
  410. static void dump_spd_ddr_reg(void)
  411. {
  412. int i, j, k, m;
  413. u8 *p_8;
  414. u32 *p_32;
  415. struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
  416. generic_spd_eeprom_t
  417. spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
  418. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
  419. fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
  420. puts("SPD data of all dimms (zero vaule is omitted)...\n");
  421. puts("Byte (hex) ");
  422. k = 1;
  423. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  424. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
  425. printf("Dimm%d ", k++);
  426. }
  427. puts("\n");
  428. for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
  429. m = 0;
  430. printf("%3d (0x%02x) ", k, k);
  431. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  432. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
  433. p_8 = (u8 *) &spd[i][j];
  434. if (p_8[k]) {
  435. printf("0x%02x ", p_8[k]);
  436. m++;
  437. } else
  438. puts(" ");
  439. }
  440. }
  441. if (m)
  442. puts("\n");
  443. else
  444. puts("\r");
  445. }
  446. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  447. switch (i) {
  448. case 0:
  449. ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  450. break;
  451. #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  452. case 1:
  453. ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  454. break;
  455. #endif
  456. #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  457. case 2:
  458. ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  459. break;
  460. #endif
  461. #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  462. case 3:
  463. ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  464. break;
  465. #endif
  466. default:
  467. printf("%s unexpected controller number = %u\n",
  468. __func__, i);
  469. return;
  470. }
  471. }
  472. printf("DDR registers dump for all controllers "
  473. "(zero vaule is omitted)...\n");
  474. puts("Offset (hex) ");
  475. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
  476. printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
  477. puts("\n");
  478. for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
  479. m = 0;
  480. printf("%6d (0x%04x)", k * 4, k * 4);
  481. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  482. p_32 = (u32 *) ddr[i];
  483. if (p_32[k]) {
  484. printf(" 0x%08x", p_32[k]);
  485. m++;
  486. } else
  487. puts(" ");
  488. }
  489. if (m)
  490. puts("\n");
  491. else
  492. puts("\r");
  493. }
  494. puts("\n");
  495. }
  496. /* invalid the TLBs for DDR and setup new ones to cover p_addr */
  497. static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
  498. {
  499. u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
  500. unsigned long epn;
  501. u32 tsize, valid, ptr;
  502. int ddr_esel;
  503. clear_ddr_tlbs_phys(p_addr, size>>20);
  504. /* Setup new tlb to cover the physical address */
  505. setup_ddr_tlbs_phys(p_addr, size>>20);
  506. ptr = vstart;
  507. ddr_esel = find_tlb_idx((void *)ptr, 1);
  508. if (ddr_esel != -1) {
  509. read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
  510. } else {
  511. printf("TLB error in function %s\n", __func__);
  512. return -1;
  513. }
  514. return 0;
  515. }
  516. /*
  517. * slide the testing window up to test another area
  518. * for 32_bit system, the maximum testable memory is limited to
  519. * CONFIG_MAX_MEM_MAPPED
  520. */
  521. int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  522. {
  523. phys_addr_t test_cap, p_addr;
  524. phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
  525. #if !defined(CONFIG_PHYS_64BIT) || \
  526. !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
  527. (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
  528. test_cap = p_size;
  529. #else
  530. test_cap = gd->ram_size;
  531. #endif
  532. p_addr = (*vstart) + (*size) + (*phys_offset);
  533. if (p_addr < test_cap - 1) {
  534. p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
  535. if (reset_tlb(p_addr, p_size, phys_offset) == -1)
  536. return -1;
  537. *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
  538. *size = (u32) p_size;
  539. printf("Testing 0x%08llx - 0x%08llx\n",
  540. (u64)(*vstart) + (*phys_offset),
  541. (u64)(*vstart) + (*phys_offset) + (*size) - 1);
  542. } else
  543. return 1;
  544. return 0;
  545. }
  546. /* initialization for testing area */
  547. int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  548. {
  549. phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
  550. *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
  551. *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
  552. *phys_offset = 0;
  553. #if !defined(CONFIG_PHYS_64BIT) || \
  554. !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
  555. (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
  556. if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
  557. puts("Cannot test more than ");
  558. print_size(CONFIG_MAX_MEM_MAPPED,
  559. " without proper 36BIT support.\n");
  560. }
  561. #endif
  562. printf("Testing 0x%08llx - 0x%08llx\n",
  563. (u64)(*vstart) + (*phys_offset),
  564. (u64)(*vstart) + (*phys_offset) + (*size) - 1);
  565. return 0;
  566. }
  567. /* invalid TLBs for DDR and remap as normal after testing */
  568. int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  569. {
  570. unsigned long epn;
  571. u32 tsize, valid, ptr;
  572. phys_addr_t rpn = 0;
  573. int ddr_esel;
  574. /* disable the TLBs for this testing */
  575. ptr = *vstart;
  576. while (ptr < (*vstart) + (*size)) {
  577. ddr_esel = find_tlb_idx((void *)ptr, 1);
  578. if (ddr_esel != -1) {
  579. read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
  580. disable_tlb(ddr_esel);
  581. }
  582. ptr += TSIZE_TO_BYTES(tsize);
  583. }
  584. puts("Remap DDR ");
  585. setup_ddr_tlbs(gd->ram_size>>20);
  586. puts("\n");
  587. return 0;
  588. }
  589. void arch_memory_failure_handle(void)
  590. {
  591. dump_spd_ddr_reg();
  592. }
  593. #endif