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@@ -18,7 +18,14 @@
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#include <asm/config_mpc85xx.h>
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#ifdef CONFIG_RAMBOOT_PBL
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+
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+#ifndef CONFIG_SECURE_BOOT
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#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
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+#else
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+#define CONFIG_SYS_FSL_PBL_PBI \
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+ $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
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+#endif
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+
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#ifdef CONFIG_T1040RDB
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#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
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#endif
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@@ -62,7 +69,17 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
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#ifdef CONFIG_NAND
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#define CONFIG_SPL_NAND_SUPPORT
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+#ifdef CONFIG_SECURE_BOOT
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+#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
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+/*
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+ * HDR would be appended at end of image and copied to DDR along
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+ * with U-Boot image.
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+ */
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+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
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+ CONFIG_U_BOOT_HDR_SIZE)
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+#else
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
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+#endif
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#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
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#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
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@@ -161,6 +178,10 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_OFFSET (512 * 0x800)
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#elif defined(CONFIG_NAND)
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+#ifdef CONFIG_SECURE_BOOT
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+#define CONFIG_RAMBOOT_NAND
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+#define CONFIG_BOOTSCRIPT_COPY_RAM
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+#endif
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_SIZE 0x2000
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@@ -202,8 +223,14 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
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* Config the L3 Cache as L3 SRAM
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*/
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#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
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+/*
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+ * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
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+ * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
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+ * (CONFIG_SYS_INIT_L3_VADDR) will be different.
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+ */
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+#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
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#define CONFIG_SYS_L3_SIZE 256 << 10
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-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
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+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
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#endif
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