tlb.c 4.5 KB

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  1. /*
  2. * Copyright 2013 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/mmu.h>
  8. struct fsl_e_tlb_entry tlb_table[] = {
  9. /* TLB 0 - for temp stack in cache */
  10. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  11. CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  12. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  13. 0, 0, BOOKE_PAGESZ_4K, 0),
  14. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  15. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  16. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  17. 0, 0, BOOKE_PAGESZ_4K, 0),
  18. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  19. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  20. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  21. 0, 0, BOOKE_PAGESZ_4K, 0),
  22. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  23. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  24. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  25. 0, 0, BOOKE_PAGESZ_4K, 0),
  26. /* TLB 1 */
  27. /* *I*** - Covers boot page */
  28. #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \
  29. !defined(CONFIG_SECURE_BOOT)
  30. /*
  31. * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
  32. * SRAM is at 0xfffc0000, it covered the 0xfffff000.
  33. */
  34. SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  35. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  36. 0, 0, BOOKE_PAGESZ_256K, 1),
  37. #elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD)
  38. /*
  39. * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot
  40. * the physical address of the SRAM is at 0xbffc0000,
  41. * and virtual address is 0xfffc0000
  42. */
  43. SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR,
  44. CONFIG_SYS_INIT_L3_ADDR,
  45. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  46. 0, 0, BOOKE_PAGESZ_256K, 1),
  47. #else
  48. SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  49. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  50. 0, 0, BOOKE_PAGESZ_4K, 1),
  51. #endif
  52. /* *I*G* - CCSRBAR */
  53. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  54. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  55. 0, 1, BOOKE_PAGESZ_16M, 1),
  56. /* *I*G* - Flash, localbus */
  57. /* This will be changed to *I*G* after relocation to RAM. */
  58. SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  59. MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  60. 0, 2, BOOKE_PAGESZ_256M, 1),
  61. #ifndef CONFIG_SPL_BUILD
  62. /* *I*G* - PCI */
  63. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  64. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  65. 0, 3, BOOKE_PAGESZ_1G, 1),
  66. /* *I*G* - PCI I/O */
  67. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  68. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  69. 0, 4, BOOKE_PAGESZ_256K, 1),
  70. /* Bman/Qman */
  71. #ifdef CONFIG_SYS_BMAN_MEM_PHYS
  72. SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  73. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  74. 0, 5, BOOKE_PAGESZ_16M, 1),
  75. SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
  76. CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
  77. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  78. 0, 6, BOOKE_PAGESZ_16M, 1),
  79. #endif
  80. #ifdef CONFIG_SYS_QMAN_MEM_PHYS
  81. SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  82. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  83. 0, 7, BOOKE_PAGESZ_16M, 1),
  84. SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
  85. CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
  86. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  87. 0, 8, BOOKE_PAGESZ_16M, 1),
  88. #endif
  89. #endif
  90. #ifdef CONFIG_SYS_DCSRBAR_PHYS
  91. SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
  92. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  93. 0, 9, BOOKE_PAGESZ_4M, 1),
  94. #endif
  95. #ifdef CONFIG_SYS_NAND_BASE
  96. /*
  97. * *I*G - NAND
  98. * entry 14 and 15 has been used hard coded, they will be disabled
  99. * in cpu_init_f, so we use entry 16 for nand.
  100. */
  101. SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  102. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  103. 0, 10, BOOKE_PAGESZ_64K, 1),
  104. #endif
  105. #ifdef CONFIG_SYS_CPLD_BASE
  106. SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
  107. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  108. 0, 11, BOOKE_PAGESZ_256K, 1),
  109. #endif
  110. #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
  111. SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  112. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  113. 0, 12, BOOKE_PAGESZ_1G, 1),
  114. SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
  115. CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
  116. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  117. 0, 13, BOOKE_PAGESZ_1G, 1)
  118. #endif
  119. };
  120. int num_tlb_entries = ARRAY_SIZE(tlb_table);