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@@ -29,6 +29,15 @@ config SYS_TEXT_BASE
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default 0x01000040 if TARGET_SOCFPGA_ARRIA10
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default 0x01000040 if TARGET_SOCFPGA_GEN5
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+config TARGET_SOCFPGA_AGILEX
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+ bool
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+ select ARMV8_MULTIENTRY
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+ select ARMV8_SET_SMPEN
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+ select ARMV8_SPIN_TABLE
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+ select CLK
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+ select NCORE_CACHE
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+ select SPL_CLK if SPL
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+
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config TARGET_SOCFPGA_ARRIA5
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bool
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select TARGET_SOCFPGA_GEN5
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@@ -75,6 +84,10 @@ choice
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prompt "Altera SOCFPGA board select"
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optional
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+config TARGET_SOCFPGA_AGILEX_SOCDK
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+ bool "Intel SOCFPGA SoCDK (Agilex)"
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+ select TARGET_SOCFPGA_AGILEX
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+
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config TARGET_SOCFPGA_ARIES_MCVEVK
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bool "Aries MCVEVK (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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@@ -135,6 +148,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
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endchoice
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config SYS_BOARD
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+ default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
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default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
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default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
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default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
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@@ -151,6 +165,7 @@ config SYS_BOARD
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default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
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config SYS_VENDOR
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+ default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
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default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
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default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
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default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
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@@ -168,6 +183,7 @@ config SYS_SOC
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default "socfpga"
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config SYS_CONFIG_NAME
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+ default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
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default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
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default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
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default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
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