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@@ -1,198 +1,12 @@
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/* SPDX-License-Identifier: GPL-2.0
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*
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- * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
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+ * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
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*
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*/
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#ifndef __CONFIG_SOCFGPA_STRATIX10_H__
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#define __CONFIG_SOCFGPA_STRATIX10_H__
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-#include <asm/arch/base_addr_s10.h>
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-#include <asm/arch/handoff_s10.h>
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+#include <configs/socfpga_soc64_common.h>
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-/*
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- * U-Boot general configurations
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- */
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-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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-#define CONFIG_LOADADDR 0x2000000
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-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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-#define CONFIG_REMAKE_ELF
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-/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
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-#define CPU_RELEASE_ADDR 0xFFD12210
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-#define CONFIG_SYS_CACHELINE_SIZE 64
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-#define CONFIG_SYS_MEM_RESERVE_SECURE 0 /* using OCRAM, not DDR */
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-
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-/*
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- * U-Boot console configurations
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- */
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-#define CONFIG_SYS_MAXARGS 64
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-#define CONFIG_SYS_CBSIZE 2048
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-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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- sizeof(CONFIG_SYS_PROMPT) + 16)
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-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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-
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-/* Extend size of kernel image for uncompression */
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-#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
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-
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-/*
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- * U-Boot run time memory configurations
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- */
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-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
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-#define CONFIG_SYS_INIT_RAM_SIZE 0x40000
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-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \
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- + CONFIG_SYS_INIT_RAM_SIZE \
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- - S10_HANDOFF_SIZE)
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-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR)
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-#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
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-
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-/*
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- * U-Boot environment configurations
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- */
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-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
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-
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-/*
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- * QSPI support
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- */
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- #ifdef CONFIG_CADENCE_QSPI
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-/* Enable it if you want to use dual-stacked mode */
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-/*#define CONFIG_QSPI_RBF_ADDR 0x720000*/
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-
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-/* Flash device info */
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-
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-/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
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-
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-#ifndef CONFIG_SPL_BUILD
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-#define CONFIG_MTD_PARTITIONS
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-#define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
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-#endif /* CONFIG_SPL_BUILD */
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-
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-#ifndef __ASSEMBLY__
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-unsigned int cm_get_qspi_controller_clk_hz(void);
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-#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
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-#endif
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-
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-#endif /* CONFIG_CADENCE_QSPI */
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-
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-/*
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- * Boot arguments passed to the boot command. The value of
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- * CONFIG_BOOTARGS goes into the environment value "bootargs".
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- * Do note the value will override also the chosen node in FDT blob.
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- */
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-#define CONFIG_BOOTARGS "earlycon"
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-#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \
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- "run mmcboot"
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-
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-#define CONFIG_EXTRA_ENV_SETTINGS \
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- "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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- "bootfile=Image\0" \
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- "fdt_addr=8000000\0" \
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- "fdtimage=socfpga_stratix10_socdk.dtb\0" \
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- "mmcroot=/dev/mmcblk0p2\0" \
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- "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
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- " root=${mmcroot} rw rootwait;" \
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- "booti ${loadaddr} - ${fdt_addr}\0" \
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- "mmcload=mmc rescan;" \
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- "load mmc 0:1 ${loadaddr} ${bootfile};" \
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- "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
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- "linux_qspi_enable=if sf probe; then " \
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- "echo Enabling QSPI at Linux DTB...;" \
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- "fdt addr ${fdt_addr}; fdt resize;" \
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- "fdt set /soc/spi@ff8d2000 status okay;" \
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- "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
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- " ${qspi_clock}; fi; \0" \
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- "scriptaddr=0x02100000\0" \
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- "scriptfile=u-boot.scr\0" \
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- "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
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- "then source ${scriptaddr}; fi\0" \
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- "socfpga_legacy_reset_compat=1\0"
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-
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-/*
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- * Generic Interrupt Controller Definitions
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- */
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-#define CONFIG_GICV2
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-
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-/*
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- * External memory configurations
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- */
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-#define PHYS_SDRAM_1 0x0
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-#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024)
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-#define CONFIG_SYS_SDRAM_BASE 0
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-#define CONFIG_SYS_MEMTEST_START 0
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-#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - 0x200000
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-
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-/*
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- * Serial / UART configurations
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- */
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-#define CONFIG_SYS_NS16550_CLK 100000000
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-#define CONFIG_SYS_NS16550_MEM32
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-
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-/*
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- * Timer & watchdog configurations
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- */
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-#define COUNTER_FREQUENCY 400000000
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-
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-/*
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- * SDMMC configurations
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- */
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-#ifdef CONFIG_CMD_MMC
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-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
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-#endif
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-/*
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- * Flash configurations
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- */
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-#define CONFIG_SYS_MAX_FLASH_BANKS 1
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-
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-/* Ethernet on SoC (EMAC) */
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-#if defined(CONFIG_CMD_NET)
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-#define CONFIG_DW_ALTDESCRIPTOR
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-#endif /* CONFIG_CMD_NET */
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-
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-/*
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- * L4 Watchdog
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- */
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-#ifdef CONFIG_SPL_BUILD
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-#define CONFIG_HW_WATCHDOG
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-#define CONFIG_DESIGNWARE_WATCHDOG
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-#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
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-#ifndef __ASSEMBLY__
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-unsigned int cm_get_l4_sys_free_clk_hz(void);
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-#define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000)
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-#endif
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-#endif
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-
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-/*
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- * SPL memory layout
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- *
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- * On chip RAM
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- * 0xFFE0_0000 ...... Start of OCRAM
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- * SPL code, rwdata
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- * empty space
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- * 0xFFEx_xxxx ...... Top of stack (grows down)
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- * 0xFFEy_yyyy ...... Global Data
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- * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
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- * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
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- * 0xFFE3_FFFF ...... End of OCRAM
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- *
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- * SDRAM
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- * 0x0000_0000 ...... Start of SDRAM_1
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- * unused / empty space for image loading
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- * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
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- * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
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- * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
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- *
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- */
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-#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex"
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-#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
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-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
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-#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
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-#define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
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- - CONFIG_SPL_BSS_MAX_SIZE)
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-#define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN)
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-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \
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- - CONFIG_SYS_SPL_MALLOC_SIZE)
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-
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-/* SPL SDMMC boot support */
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-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
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-
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-#endif /* __CONFIG_H */
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+#endif /* __CONFIG_SOCFGPA_STRATIX10_H__ */
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