socfpga_soc64_common.h 5.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
  7. #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
  8. #include <asm/arch/base_addr_s10.h>
  9. #include <asm/arch/handoff_s10.h>
  10. /*
  11. * U-Boot general configurations
  12. */
  13. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  14. #define CONFIG_LOADADDR 0x2000000
  15. #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  16. #define CONFIG_REMAKE_ELF
  17. /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  18. #define CPU_RELEASE_ADDR 0xFFD12210
  19. #define CONFIG_SYS_CACHELINE_SIZE 64
  20. #define CONFIG_SYS_MEM_RESERVE_SECURE 0 /* using OCRAM, not DDR */
  21. /*
  22. * U-Boot console configurations
  23. */
  24. #define CONFIG_SYS_MAXARGS 64
  25. #define CONFIG_SYS_CBSIZE 2048
  26. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  27. sizeof(CONFIG_SYS_PROMPT) + 16)
  28. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  29. /* Extend size of kernel image for uncompression */
  30. #define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
  31. /*
  32. * U-Boot run time memory configurations
  33. */
  34. #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
  35. #define CONFIG_SYS_INIT_RAM_SIZE 0x40000
  36. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \
  37. + CONFIG_SYS_INIT_RAM_SIZE \
  38. - S10_HANDOFF_SIZE)
  39. #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR)
  40. #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
  41. /*
  42. * U-Boot environment configurations
  43. */
  44. #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
  45. /*
  46. * QSPI support
  47. */
  48. #ifdef CONFIG_CADENCE_QSPI
  49. /* Enable it if you want to use dual-stacked mode */
  50. /*#define CONFIG_QSPI_RBF_ADDR 0x720000*/
  51. /* Flash device info */
  52. /*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
  53. #ifndef CONFIG_SPL_BUILD
  54. #define CONFIG_MTD_DEVICE
  55. #define CONFIG_MTD_PARTITIONS
  56. #define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
  57. #endif /* CONFIG_SPL_BUILD */
  58. #ifndef __ASSEMBLY__
  59. unsigned int cm_get_qspi_controller_clk_hz(void);
  60. #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
  61. #endif
  62. #endif /* CONFIG_CADENCE_QSPI */
  63. /*
  64. * Boot arguments passed to the boot command. The value of
  65. * CONFIG_BOOTARGS goes into the environment value "bootargs".
  66. * Do note the value will override also the chosen node in FDT blob.
  67. */
  68. #define CONFIG_BOOTARGS "earlycon"
  69. #define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \
  70. "run mmcboot"
  71. #define CONFIG_EXTRA_ENV_SETTINGS \
  72. "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  73. "bootfile=Image\0" \
  74. "fdt_addr=8000000\0" \
  75. "fdtimage=socfpga_stratix10_socdk.dtb\0" \
  76. "mmcroot=/dev/mmcblk0p2\0" \
  77. "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  78. " root=${mmcroot} rw rootwait;" \
  79. "booti ${loadaddr} - ${fdt_addr}\0" \
  80. "mmcload=mmc rescan;" \
  81. "load mmc 0:1 ${loadaddr} ${bootfile};" \
  82. "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  83. "linux_qspi_enable=if sf probe; then " \
  84. "echo Enabling QSPI at Linux DTB...;" \
  85. "fdt addr ${fdt_addr}; fdt resize;" \
  86. "fdt set /soc/spi@ff8d2000 status okay;" \
  87. "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
  88. " ${qspi_clock}; fi; \0" \
  89. "scriptaddr=0x02100000\0" \
  90. "scriptfile=u-boot.scr\0" \
  91. "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
  92. "then source ${scriptaddr}; fi\0" \
  93. "socfpga_legacy_reset_compat=1\0"
  94. /*
  95. * Generic Interrupt Controller Definitions
  96. */
  97. #define CONFIG_GICV2
  98. /*
  99. * External memory configurations
  100. */
  101. #define PHYS_SDRAM_1 0x0
  102. #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024)
  103. #define CONFIG_SYS_SDRAM_BASE 0
  104. #define CONFIG_SYS_MEMTEST_START 0
  105. #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - 0x200000
  106. /*
  107. * Serial / UART configurations
  108. */
  109. #define CONFIG_SYS_NS16550_CLK 100000000
  110. #define CONFIG_SYS_NS16550_MEM32
  111. /*
  112. * Timer & watchdog configurations
  113. */
  114. #define COUNTER_FREQUENCY 400000000
  115. /*
  116. * SDMMC configurations
  117. */
  118. #ifdef CONFIG_CMD_MMC
  119. #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
  120. #endif
  121. /*
  122. * Flash configurations
  123. */
  124. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  125. /* Ethernet on SoC (EMAC) */
  126. #if defined(CONFIG_CMD_NET)
  127. #define CONFIG_DW_ALTDESCRIPTOR
  128. #endif /* CONFIG_CMD_NET */
  129. /*
  130. * L4 Watchdog
  131. */
  132. #ifdef CONFIG_SPL_BUILD
  133. #define CONFIG_HW_WATCHDOG
  134. #define CONFIG_DESIGNWARE_WATCHDOG
  135. #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
  136. #ifndef __ASSEMBLY__
  137. unsigned int cm_get_l4_sys_free_clk_hz(void);
  138. #define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000)
  139. #endif
  140. #endif
  141. /*
  142. * SPL memory layout
  143. *
  144. * On chip RAM
  145. * 0xFFE0_0000 ...... Start of OCRAM
  146. * SPL code, rwdata
  147. * empty space
  148. * 0xFFEx_xxxx ...... Top of stack (grows down)
  149. * 0xFFEy_yyyy ...... Global Data
  150. * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
  151. * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
  152. * 0xFFE3_FFFF ...... End of OCRAM
  153. *
  154. * SDRAM
  155. * 0x0000_0000 ...... Start of SDRAM_1
  156. * unused / empty space for image loading
  157. * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
  158. * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
  159. * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
  160. *
  161. */
  162. #define CONFIG_SPL_TARGET "spl/u-boot-spl.hex"
  163. #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
  164. #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
  165. #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
  166. #define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
  167. - CONFIG_SPL_BSS_MAX_SIZE)
  168. #define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN)
  169. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \
  170. - CONFIG_SYS_SPL_MALLOC_SIZE)
  171. /* SPL SDMMC boot support */
  172. #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  173. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  174. #endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */