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@@ -0,0 +1,158 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (C) 2019 MediaTek Inc. All Rights Reserved.
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+ *
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+ * Author: Weijie Gao <weijie.gao@mediatek.com>
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+ */
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+
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+#include <common.h>
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+#include <clk-uclass.h>
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+#include <dm.h>
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+#include <dt-bindings/clock/mt7628-clk.h>
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+#include <linux/bitops.h>
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+#include <linux/io.h>
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+
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+/* SYSCFG0 */
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+#define XTAL_40M_SEL BIT(6)
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+
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+/* CLKCFG0 */
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+#define CLKCFG0_REG 0x0
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+#define PERI_CLK_FROM_XTAL_SEL BIT(4)
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+#define CPU_PLL_FROM_BBP BIT(1)
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+#define CPU_PLL_FROM_XTAL BIT(0)
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+
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+/* CLKCFG1 */
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+#define CLKCFG1_REG 0x4
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+
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+#define CLK_SRC_CPU -1
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+#define CLK_SRC_CPU_D2 -2
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+#define CLK_SRC_SYS -3
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+#define CLK_SRC_XTAL -4
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+#define CLK_SRC_PERI -5
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+
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+struct mt7628_clk_priv {
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+ void __iomem *base;
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+ int cpu_clk;
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+ int sys_clk;
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+ int xtal_clk;
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+};
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+
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+static const int mt7628_clks[] = {
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+ [CLK_SYS] = CLK_SRC_SYS,
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+ [CLK_CPU] = CLK_SRC_CPU,
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+ [CLK_XTAL] = CLK_SRC_XTAL,
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+ [CLK_PWM] = CLK_SRC_PERI,
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+ [CLK_MIPS_CNT] = CLK_SRC_CPU_D2,
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+ [CLK_UART2] = CLK_SRC_PERI,
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+ [CLK_UART1] = CLK_SRC_PERI,
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+ [CLK_UART0] = CLK_SRC_PERI,
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+ [CLK_SPI] = CLK_SRC_SYS,
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+ [CLK_I2C] = CLK_SRC_PERI,
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+};
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+
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+static ulong mt7628_clk_get_rate(struct clk *clk)
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+{
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+ struct mt7628_clk_priv *priv = dev_get_priv(clk->dev);
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+ u32 val;
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+
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+ if (clk->id >= ARRAY_SIZE(mt7628_clks))
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+ return 0;
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+
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+ switch (mt7628_clks[clk->id]) {
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+ case CLK_SRC_CPU:
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+ return priv->cpu_clk;
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+ case CLK_SRC_CPU_D2:
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+ return priv->cpu_clk / 2;
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+ case CLK_SRC_SYS:
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+ return priv->sys_clk;
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+ case CLK_SRC_XTAL:
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+ return priv->xtal_clk;
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+ case CLK_SRC_PERI:
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+ val = readl(priv->base + CLKCFG0_REG);
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+ if (val & PERI_CLK_FROM_XTAL_SEL)
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+ return priv->xtal_clk;
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+ else
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+ return 40000000;
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+ default:
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+ return mt7628_clks[clk->id];
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+ }
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+}
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+
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+static int mt7628_clk_enable(struct clk *clk)
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+{
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+ struct mt7628_clk_priv *priv = dev_get_priv(clk->dev);
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+
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+ if (clk->id > 31)
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+ return -1;
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+
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+ setbits_32(priv->base + CLKCFG1_REG, BIT(clk->id));
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+
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+ return 0;
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+}
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+
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+static int mt7628_clk_disable(struct clk *clk)
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+{
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+ struct mt7628_clk_priv *priv = dev_get_priv(clk->dev);
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+
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+ if (clk->id > 31)
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+ return -1;
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+
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+ clrbits_32(priv->base + CLKCFG1_REG, BIT(clk->id));
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+
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+ return 0;
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+}
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+
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+const struct clk_ops mt7628_clk_ops = {
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+ .enable = mt7628_clk_enable,
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+ .disable = mt7628_clk_disable,
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+ .get_rate = mt7628_clk_get_rate,
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+};
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+
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+static int mt7628_clk_probe(struct udevice *dev)
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+{
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+ struct mt7628_clk_priv *priv = dev_get_priv(dev);
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+ void __iomem *syscfg_base;
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+ u32 val;
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+
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+ priv->base = (void __iomem *)dev_remap_addr_index(dev, 0);
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+ if (!priv->base)
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+ return -EINVAL;
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+
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+ syscfg_base = (void __iomem *)dev_remap_addr_index(dev, 1);
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+ if (!syscfg_base)
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+ return -EINVAL;
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+
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+ val = readl(syscfg_base);
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+ if (val & XTAL_40M_SEL)
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+ priv->xtal_clk = 40000000;
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+ else
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+ priv->xtal_clk = 25000000;
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+
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+ val = readl(priv->base + CLKCFG0_REG);
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+ if (val & CPU_PLL_FROM_BBP)
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+ priv->cpu_clk = 480000000;
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+ else if (val & CPU_PLL_FROM_XTAL)
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+ priv->cpu_clk = priv->xtal_clk;
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+ else if (priv->xtal_clk == 40000000)
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+ priv->cpu_clk = 580000000; /* (xtal_freq / 2) * 29 */
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+ else
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+ priv->cpu_clk = 575000000; /* xtal_freq * 23 */
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+
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+ priv->sys_clk = priv->cpu_clk / 3;
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+
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+ return 0;
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+}
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+
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+static const struct udevice_id mt7628_clk_ids[] = {
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+ { .compatible = "mediatek,mt7628-clk" },
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+ { }
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+};
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+
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+U_BOOT_DRIVER(mt7628_clk) = {
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+ .name = "mt7628-clk",
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+ .id = UCLASS_CLK,
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+ .of_match = mt7628_clk_ids,
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+ .probe = mt7628_clk_probe,
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+ .priv_auto_alloc_size = sizeof(struct mt7628_clk_priv),
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+ .ops = &mt7628_clk_ops,
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+};
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