mt7628-clk.h 781 B

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2019 MediaTek Inc.
  4. *
  5. * Author: Weijie Gao <weijie.gao@mediatek.com>
  6. */
  7. #ifndef _DT_BINDINGS_MT7628_CLK_H_
  8. #define _DT_BINDINGS_MT7628_CLK_H_
  9. /* Base clocks */
  10. #define CLK_SYS 34
  11. #define CLK_CPU 33
  12. #define CLK_XTAL 32
  13. /* Peripheral clocks */
  14. #define CLK_PWM 31
  15. #define CLK_SDXC 30
  16. #define CLK_CRYPTO 29
  17. #define CLK_MIPS_CNT 28
  18. #define CLK_PCIE 26
  19. #define CLK_UPHY 25
  20. #define CLK_ETH 23
  21. #define CLK_UART2 20
  22. #define CLK_UART1 19
  23. #define CLK_SPI 18
  24. #define CLK_I2S 17
  25. #define CLK_I2C 16
  26. #define CLK_GDMA 14
  27. #define CLK_PIO 13
  28. #define CLK_UART0 12
  29. #define CLK_PCM 11
  30. #define CLK_MC 10
  31. #define CLK_INTC 9
  32. #define CLK_TIMER 8
  33. #endif /* _DT_BINDINGS_MT7628_CLK_H_ */