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@@ -1,13 +1,12 @@
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-// SPDX-License-Identifier: GPL-2.0+
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+// SPDX-License-Identifier: GPL-2.0
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/*
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- * Renesas R8A7795 CPG MSSR driver
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+ * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
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*
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- * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
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+ * Copyright (C) 2015 Glider bvba
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*
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- * Based on the following driver from Linux kernel:
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- * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
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+ * Based on clk-rcar-gen3.c
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*
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- * Copyright (C) 2016 Glider bvba
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+ * Copyright (C) 2015 Renesas Electronics Corp.
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*/
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#include <common.h>
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@@ -71,7 +70,11 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
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+ DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
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+
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/* Core Clock Outputs */
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+ DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
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+ DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
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DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
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DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
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@@ -101,9 +104,16 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
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DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238),
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DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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+ DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1),
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DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
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+ DEF_FIXED("cpex", R8A7795_CLK_CPEX, CLK_EXTAL, 2, 1),
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+
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+ DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
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+ DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
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+ DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
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+ DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
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- /* NOTE: HDMI, CSI, CAN etc. clock are missing */
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+ DEF_GEN3_OSC("osc", R8A7795_CLK_OSC, CLK_EXTAL, 8),
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DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
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};
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@@ -124,6 +134,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
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DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
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DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
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DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
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+ DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR),
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DEF_MOD("cmt3", 300, R8A7795_CLK_R),
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DEF_MOD("cmt2", 301, R8A7795_CLK_R),
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DEF_MOD("cmt1", 302, R8A7795_CLK_R),
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@@ -143,7 +154,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
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DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
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DEF_MOD("rwdt", 402, R8A7795_CLK_R),
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DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
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- DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
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+ DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
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DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3),
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DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3),
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DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
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@@ -269,25 +280,25 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
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*/
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/*
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- * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
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+ * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
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* 14 13 19 17 (MHz)
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- *-------------------------------------------------------------------
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- * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
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- * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
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+ *-------------------------------------------------------------------------
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+ * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
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+ * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
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* 0 0 1 0 Prohibited setting
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- * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
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- * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
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- * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
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+ * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
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+ * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
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+ * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
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* 0 1 1 0 Prohibited setting
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- * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
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- * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
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- * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
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+ * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
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+ * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
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+ * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
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* 1 0 1 0 Prohibited setting
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- * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
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- * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
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- * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
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+ * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
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+ * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
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+ * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
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* 1 1 1 0 Prohibited setting
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- * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
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+ * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
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*/
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#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
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(((md) & BIT(13)) >> 11) | \
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@@ -295,23 +306,23 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
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(((md) & BIT(17)) >> 17))
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static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
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- /* EXTAL div PLL1 mult/div PLL3 mult/div */
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- { 1, 192, 1, 192, 1, },
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- { 1, 192, 1, 128, 1, },
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- { 0, /* Prohibited setting */ },
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- { 1, 192, 1, 192, 1, },
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- { 1, 160, 1, 160, 1, },
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- { 1, 160, 1, 106, 1, },
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- { 0, /* Prohibited setting */ },
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- { 1, 160, 1, 160, 1, },
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- { 1, 128, 1, 128, 1, },
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- { 1, 128, 1, 84, 1, },
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- { 0, /* Prohibited setting */ },
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- { 1, 128, 1, 128, 1, },
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- { 2, 192, 1, 192, 1, },
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- { 2, 192, 1, 128, 1, },
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- { 0, /* Prohibited setting */ },
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- { 2, 192, 1, 192, 1, },
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+ /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
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+ { 1, 192, 1, 192, 1, 16, },
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+ { 1, 192, 1, 128, 1, 16, },
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+ { 0, /* Prohibited setting */ },
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+ { 1, 192, 1, 192, 1, 16, },
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+ { 1, 160, 1, 160, 1, 19, },
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+ { 1, 160, 1, 106, 1, 19, },
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+ { 0, /* Prohibited setting */ },
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+ { 1, 160, 1, 160, 1, 19, },
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+ { 1, 128, 1, 128, 1, 24, },
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+ { 1, 128, 1, 84, 1, 24, },
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+ { 0, /* Prohibited setting */ },
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+ { 1, 128, 1, 128, 1, 24, },
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+ { 2, 192, 1, 192, 1, 32, },
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+ { 2, 192, 1, 128, 1, 32, },
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+ { 0, /* Prohibited setting */ },
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+ { 2, 192, 1, 192, 1, 32, },
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};
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static const struct mstp_stop_table r8a7795_mstp_table[] = {
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