|
@@ -1,4 +1,4 @@
|
|
|
-// SPDX-License-Identifier: GPL-2.0+
|
|
|
+// SPDX-License-Identifier: GPL-2.0
|
|
|
/*
|
|
|
* Renesas R8A7791 CPG MSSR driver
|
|
|
*
|
|
@@ -6,8 +6,11 @@
|
|
|
*
|
|
|
* Based on the following driver from Linux kernel:
|
|
|
* r8a7791 Clock Pulse Generator / Module Standby and Software Reset
|
|
|
+ *
|
|
|
* Copyright (C) 2015-2017 Glider bvba
|
|
|
+ *
|
|
|
* Based on clk-rcar-gen2.c
|
|
|
+ *
|
|
|
* Copyright (C) 2013 Ideas On Board SPRL
|
|
|
*/
|
|
|
|
|
@@ -54,7 +57,6 @@ static const struct cpg_core_clk r8a7791_core_clks[] = {
|
|
|
|
|
|
/* Core Clock Outputs */
|
|
|
DEF_BASE("z", R8A7791_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
|
|
|
- DEF_BASE("lb", R8A7791_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
|
|
|
DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
|
|
|
DEF_BASE("sdh", R8A7791_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
|
|
|
DEF_BASE("sd0", R8A7791_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
|
|
@@ -67,6 +69,7 @@ static const struct cpg_core_clk r8a7791_core_clks[] = {
|
|
|
DEF_FIXED("hp", R8A7791_CLK_HP, CLK_PLL1, 12, 1),
|
|
|
DEF_FIXED("i", R8A7791_CLK_I, CLK_PLL1, 2, 1),
|
|
|
DEF_FIXED("b", R8A7791_CLK_B, CLK_PLL1, 12, 1),
|
|
|
+ DEF_FIXED("lb", R8A7791_CLK_LB, CLK_PLL1, 24, 1),
|
|
|
DEF_FIXED("p", R8A7791_CLK_P, CLK_PLL1, 24, 1),
|
|
|
DEF_FIXED("cl", R8A7791_CLK_CL, CLK_PLL1, 48, 1),
|
|
|
DEF_FIXED("m2", R8A7791_CLK_M2, CLK_PLL1, 8, 1),
|
|
@@ -125,6 +128,7 @@ static const struct mssr_mod_clk r8a7791_mod_clks[] = {
|
|
|
DEF_MOD("cmt1", 329, R8A7791_CLK_R),
|
|
|
DEF_MOD("usbhs-dmac0", 330, R8A7791_CLK_HP),
|
|
|
DEF_MOD("usbhs-dmac1", 331, R8A7791_CLK_HP),
|
|
|
+ DEF_MOD("rwdt", 402, R8A7791_CLK_R),
|
|
|
DEF_MOD("irqc", 407, R8A7791_CLK_CP),
|
|
|
DEF_MOD("intc-sys", 408, R8A7791_CLK_ZS),
|
|
|
DEF_MOD("audio-dmac1", 501, R8A7791_CLK_HP),
|