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@@ -0,0 +1,216 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Uclass for Primary-to-sideband bus, used to access various peripherals
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+ *
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+ * Copyright 2019 Google LLC
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+ * Written by Simon Glass <sjg@chromium.org>
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+ */
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+
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+#include <common.h>
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+#include <dm.h>
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+#include <mapmem.h>
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+#include <p2sb.h>
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+#include <spl.h>
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+#include <asm/io.h>
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+#include <dm/uclass-internal.h>
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+
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+#define PCR_COMMON_IOSF_1_0 1
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+
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+static void *_pcr_reg_address(struct udevice *dev, uint offset)
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+{
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+ struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
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+ struct udevice *p2sb = dev_get_parent(dev);
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+ struct p2sb_uc_priv *upriv = dev_get_uclass_priv(p2sb);
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+ uintptr_t reg_addr;
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+
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+ /* Create an address based off of port id and offset */
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+ reg_addr = upriv->mmio_base;
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+ reg_addr += pplat->pid << PCR_PORTID_SHIFT;
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+ reg_addr += offset;
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+
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+ return map_sysmem(reg_addr, 4);
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+}
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+
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+/*
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+ * The mapping of addresses via the SBREG_BAR assumes the IOSF-SB
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+ * agents are using 32-bit aligned accesses for their configuration
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+ * registers. For IOSF versions greater than 1_0, IOSF-SB
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+ * agents can use any access (8/16/32 bit aligned) for their
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+ * configuration registers
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+ */
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+static inline void check_pcr_offset_align(uint offset, uint size)
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+{
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+ const size_t align = PCR_COMMON_IOSF_1_0 ? sizeof(uint32_t) : size;
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+
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+ assert(IS_ALIGNED(offset, align));
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+}
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+
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+uint pcr_read32(struct udevice *dev, uint offset)
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+{
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+ void *ptr;
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+ uint val;
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+
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+ /* Ensure the PCR offset is correctly aligned */
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+ assert(IS_ALIGNED(offset, sizeof(uint32_t)));
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+
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+ ptr = _pcr_reg_address(dev, offset);
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+ val = readl(ptr);
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+ unmap_sysmem(ptr);
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+
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+ return val;
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+}
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+
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+uint pcr_read16(struct udevice *dev, uint offset)
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+{
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+ /* Ensure the PCR offset is correctly aligned */
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+ check_pcr_offset_align(offset, sizeof(uint16_t));
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+
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+ return readw(_pcr_reg_address(dev, offset));
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+}
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+
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+uint pcr_read8(struct udevice *dev, uint offset)
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+{
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+ /* Ensure the PCR offset is correctly aligned */
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+ check_pcr_offset_align(offset, sizeof(uint8_t));
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+
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+ return readb(_pcr_reg_address(dev, offset));
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+}
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+
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+/*
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+ * After every write one needs to perform a read an innocuous register to
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+ * ensure the writes are completed for certain ports. This is done for
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+ * all ports so that the callers don't need the per-port knowledge for
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+ * each transaction.
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+ */
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+static void write_completion(struct udevice *dev, uint offset)
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+{
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+ readl(_pcr_reg_address(dev, ALIGN_DOWN(offset, sizeof(uint32_t))));
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+}
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+
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+void pcr_write32(struct udevice *dev, uint offset, uint indata)
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+{
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+ /* Ensure the PCR offset is correctly aligned */
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+ assert(IS_ALIGNED(offset, sizeof(indata)));
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+
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+ writel(indata, _pcr_reg_address(dev, offset));
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+ /* Ensure the writes complete */
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+ write_completion(dev, offset);
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+}
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+
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+void pcr_write16(struct udevice *dev, uint offset, uint indata)
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+{
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+ /* Ensure the PCR offset is correctly aligned */
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+ check_pcr_offset_align(offset, sizeof(uint16_t));
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+
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+ writew(indata, _pcr_reg_address(dev, offset));
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+ /* Ensure the writes complete */
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+ write_completion(dev, offset);
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+}
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+
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+void pcr_write8(struct udevice *dev, uint offset, uint indata)
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+{
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+ /* Ensure the PCR offset is correctly aligned */
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+ check_pcr_offset_align(offset, sizeof(uint8_t));
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+
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+ writeb(indata, _pcr_reg_address(dev, offset));
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+ /* Ensure the writes complete */
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+ write_completion(dev, offset);
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+}
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+
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+void pcr_clrsetbits32(struct udevice *dev, uint offset, uint clr, uint set)
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+{
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+ uint data32;
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+
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+ data32 = pcr_read32(dev, offset);
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+ data32 &= ~clr;
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+ data32 |= set;
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+ pcr_write32(dev, offset, data32);
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+}
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+
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+void pcr_clrsetbits16(struct udevice *dev, uint offset, uint clr, uint set)
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+{
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+ uint data16;
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+
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+ data16 = pcr_read16(dev, offset);
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+ data16 &= ~clr;
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+ data16 |= set;
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+ pcr_write16(dev, offset, data16);
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+}
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+
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+void pcr_clrsetbits8(struct udevice *dev, uint offset, uint clr, uint set)
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+{
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+ uint data8;
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+
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+ data8 = pcr_read8(dev, offset);
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+ data8 &= ~clr;
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+ data8 |= set;
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+ pcr_write8(dev, offset, data8);
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+}
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+
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+int p2sb_get_port_id(struct udevice *dev)
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+{
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+ struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
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+
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+ return pplat->pid;
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+}
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+
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+int p2sb_set_port_id(struct udevice *dev, int portid)
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+{
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+ struct udevice *ps2b;
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+ struct p2sb_child_platdata *pplat;
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+
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+ if (!CONFIG_IS_ENABLED(OF_PLATDATA))
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+ return -ENOSYS;
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+
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+ uclass_find_first_device(UCLASS_P2SB, &ps2b);
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+ if (!ps2b)
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+ return -EDEADLK;
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+ dev->parent = ps2b;
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+
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+ /*
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+ * We must allocate this, since when the device was bound it did not
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+ * have a parent.
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+ * TODO(sjg@chromium.org): Add a parent pointer to child devices in dtoc
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+ */
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+ dev->parent_platdata = malloc(sizeof(*pplat));
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+ if (!dev->parent_platdata)
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+ return -ENOMEM;
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+ pplat = dev_get_parent_platdata(dev);
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+ pplat->pid = portid;
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+
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+ return 0;
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+}
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+
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+static int p2sb_child_post_bind(struct udevice *dev)
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+{
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+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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+ struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
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+ int ret;
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+ u32 pid;
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+
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+ ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
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+ if (ret)
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+ return ret;
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+ pplat->pid = pid;
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+#endif
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+
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+ return 0;
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+}
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+
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+static int p2sb_post_bind(struct udevice *dev)
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+{
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+ if (spl_phase() > PHASE_TPL && !CONFIG_IS_ENABLED(OF_PLATDATA))
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+ return dm_scan_fdt_dev(dev);
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+
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+ return 0;
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+}
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+
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+UCLASS_DRIVER(p2sb) = {
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+ .id = UCLASS_P2SB,
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+ .name = "p2sb",
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+ .per_device_auto_alloc_size = sizeof(struct p2sb_uc_priv),
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+ .post_bind = p2sb_post_bind,
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+ .child_post_bind = p2sb_child_post_bind,
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+ .per_child_platdata_auto_alloc_size =
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+ sizeof(struct p2sb_child_platdata),
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+};
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