Kconfig 16 KB

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  1. #
  2. # Multifunction miscellaneous devices
  3. #
  4. menu "Multifunction device drivers"
  5. config MISC
  6. bool "Enable Driver Model for Misc drivers"
  7. depends on DM
  8. help
  9. Enable driver model for miscellaneous devices. This class is
  10. used only for those do not fit other more general classes. A
  11. set of generic read, write and ioctl methods may be used to
  12. access the device.
  13. config SPL_MISC
  14. bool "Enable Driver Model for Misc drivers in SPL"
  15. depends on SPL_DM
  16. help
  17. Enable driver model for miscellaneous devices. This class is
  18. used only for those do not fit other more general classes. A
  19. set of generic read, write and ioctl methods may be used to
  20. access the device.
  21. config TPL_MISC
  22. bool "Enable Driver Model for Misc drivers in TPL"
  23. depends on TPL_DM
  24. help
  25. Enable driver model for miscellaneous devices. This class is
  26. used only for those do not fit other more general classes. A
  27. set of generic read, write and ioctl methods may be used to
  28. access the device.
  29. config ALTERA_SYSID
  30. bool "Altera Sysid support"
  31. depends on MISC
  32. help
  33. Select this to enable a sysid for Altera devices. Please find
  34. details on the "Embedded Peripherals IP User Guide" of Altera.
  35. config ATSHA204A
  36. bool "Support for Atmel ATSHA204A module"
  37. depends on MISC
  38. help
  39. Enable support for I2C connected Atmel's ATSHA204A
  40. CryptoAuthentication module found for example on the Turris Omnia
  41. board.
  42. config ROCKCHIP_EFUSE
  43. bool "Rockchip e-fuse support"
  44. depends on MISC
  45. help
  46. Enable (read-only) access for the e-fuse block found in Rockchip
  47. SoCs: accesses can either be made using byte addressing and a length
  48. or through child-nodes that are generated based on the e-fuse map
  49. retrieved from the DTS.
  50. This driver currently supports the RK3399 only, but can easily be
  51. extended (by porting the read function from the Linux kernel sources)
  52. to support other recent Rockchip devices.
  53. config ROCKCHIP_OTP
  54. bool "Rockchip OTP Support"
  55. depends on MISC
  56. help
  57. Enable (read-only) access for the one-time-programmable memory block
  58. found in Rockchip SoCs: accesses can either be made using byte
  59. addressing and a length or through child-nodes that are generated
  60. based on the e-fuse map retrieved from the DTS.
  61. config VEXPRESS_CONFIG
  62. bool "Enable support for Arm Versatile Express config bus"
  63. depends on MISC
  64. help
  65. If you say Y here, you will get support for accessing the
  66. configuration bus on the Arm Versatile Express boards via
  67. a sysreg driver.
  68. config CMD_CROS_EC
  69. bool "Enable crosec command"
  70. depends on CROS_EC
  71. help
  72. Enable command-line access to the Chrome OS EC (Embedded
  73. Controller). This provides the 'crosec' command which has
  74. a number of sub-commands for performing EC tasks such as
  75. updating its flash, accessing a small saved context area
  76. and talking to the I2C bus behind the EC (if there is one).
  77. config CROS_EC
  78. bool "Enable Chrome OS EC"
  79. help
  80. Enable access to the Chrome OS EC. This is a separate
  81. microcontroller typically available on a SPI bus on Chromebooks. It
  82. provides access to the keyboard, some internal storage and may
  83. control access to the battery and main PMIC depending on the
  84. device. You can use the 'crosec' command to access it.
  85. config SPL_CROS_EC
  86. bool "Enable Chrome OS EC in SPL"
  87. depends on SPL
  88. help
  89. Enable access to the Chrome OS EC in SPL. This is a separate
  90. microcontroller typically available on a SPI bus on Chromebooks. It
  91. provides access to the keyboard, some internal storage and may
  92. control access to the battery and main PMIC depending on the
  93. device. You can use the 'crosec' command to access it.
  94. config TPL_CROS_EC
  95. bool "Enable Chrome OS EC in TPL"
  96. depends on TPL
  97. help
  98. Enable access to the Chrome OS EC in TPL. This is a separate
  99. microcontroller typically available on a SPI bus on Chromebooks. It
  100. provides access to the keyboard, some internal storage and may
  101. control access to the battery and main PMIC depending on the
  102. device. You can use the 'crosec' command to access it.
  103. config CROS_EC_I2C
  104. bool "Enable Chrome OS EC I2C driver"
  105. depends on CROS_EC
  106. help
  107. Enable I2C access to the Chrome OS EC. This is used on older
  108. ARM Chromebooks such as snow and spring before the standard bus
  109. changed to SPI. The EC will accept commands across the I2C using
  110. a special message protocol, and provide responses.
  111. config CROS_EC_LPC
  112. bool "Enable Chrome OS EC LPC driver"
  113. depends on CROS_EC
  114. help
  115. Enable I2C access to the Chrome OS EC. This is used on x86
  116. Chromebooks such as link and falco. The keyboard is provided
  117. through a legacy port interface, so on x86 machines the main
  118. function of the EC is power and thermal management.
  119. config SPL_CROS_EC_LPC
  120. bool "Enable Chrome OS EC LPC driver in SPL"
  121. depends on CROS_EC
  122. help
  123. Enable I2C access to the Chrome OS EC. This is used on x86
  124. Chromebooks such as link and falco. The keyboard is provided
  125. through a legacy port interface, so on x86 machines the main
  126. function of the EC is power and thermal management.
  127. config TPL_CROS_EC_LPC
  128. bool "Enable Chrome OS EC LPC driver in TPL"
  129. depends on CROS_EC
  130. help
  131. Enable I2C access to the Chrome OS EC. This is used on x86
  132. Chromebooks such as link and falco. The keyboard is provided
  133. through a legacy port interface, so on x86 machines the main
  134. function of the EC is power and thermal management.
  135. config CROS_EC_SANDBOX
  136. bool "Enable Chrome OS EC sandbox driver"
  137. depends on CROS_EC && SANDBOX
  138. help
  139. Enable a sandbox emulation of the Chrome OS EC. This supports
  140. keyboard (use the -l flag to enable the LCD), verified boot context,
  141. EC flash read/write/erase support and a few other things. It is
  142. enough to perform a Chrome OS verified boot on sandbox.
  143. config SPL_CROS_EC_SANDBOX
  144. bool "Enable Chrome OS EC sandbox driver in SPL"
  145. depends on SPL_CROS_EC && SANDBOX
  146. help
  147. Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
  148. keyboard (use the -l flag to enable the LCD), verified boot context,
  149. EC flash read/write/erase support and a few other things. It is
  150. enough to perform a Chrome OS verified boot on sandbox.
  151. config TPL_CROS_EC_SANDBOX
  152. bool "Enable Chrome OS EC sandbox driver in TPL"
  153. depends on TPL_CROS_EC && SANDBOX
  154. help
  155. Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
  156. keyboard (use the -l flag to enable the LCD), verified boot context,
  157. EC flash read/write/erase support and a few other things. It is
  158. enough to perform a Chrome OS verified boot on sandbox.
  159. config CROS_EC_SPI
  160. bool "Enable Chrome OS EC SPI driver"
  161. depends on CROS_EC
  162. help
  163. Enable SPI access to the Chrome OS EC. This is used on newer
  164. ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
  165. provides a faster and more robust interface than I2C but the bugs
  166. are less interesting.
  167. config DS4510
  168. bool "Enable support for DS4510 CPU supervisor"
  169. help
  170. Enable support for the Maxim DS4510 CPU supervisor. It has an
  171. integrated 64-byte EEPROM, four programmable non-volatile I/O pins
  172. and a configurable timer for the supervisor function. The device is
  173. connected over I2C.
  174. config FSL_SEC_MON
  175. bool "Enable FSL SEC_MON Driver"
  176. help
  177. Freescale Security Monitor block is responsible for monitoring
  178. system states.
  179. Security Monitor can be transitioned on any security failures,
  180. like software violations or hardware security violations.
  181. config JZ4780_EFUSE
  182. bool "Ingenic JZ4780 eFUSE support"
  183. depends on ARCH_JZ47XX
  184. help
  185. This selects support for the eFUSE on Ingenic JZ4780 SoCs.
  186. config MXC_OCOTP
  187. bool "Enable MXC OCOTP Driver"
  188. depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
  189. default y
  190. help
  191. If you say Y here, you will get support for the One Time
  192. Programmable memory pages that are stored on the some
  193. Freescale i.MX processors.
  194. config NUVOTON_NCT6102D
  195. bool "Enable Nuvoton NCT6102D Super I/O driver"
  196. help
  197. If you say Y here, you will get support for the Nuvoton
  198. NCT6102D Super I/O driver. This can be used to enable or
  199. disable the legacy UART, the watchdog or other devices
  200. in the Nuvoton Super IO chips on X86 platforms.
  201. config P2SB
  202. bool "Intel Primary-to-Sideband Bus"
  203. depends on X86 || SANDBOX
  204. help
  205. This enables support for the Intel Primary-to-Sideband bus,
  206. abbreviated to P2SB. The P2SB is used to access various peripherals
  207. such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
  208. space. The space is segmented into different channels and peripherals
  209. are accessed by device-specific means within those channels. Devices
  210. should be added in the device tree as subnodes of the P2SB. A
  211. Peripheral Channel Register? (PCR) API is provided to access those
  212. devices - see pcr_readl(), etc.
  213. config SPL_P2SB
  214. bool "Intel Primary-to-Sideband Bus in SPL"
  215. depends on SPL && (X86 || SANDBOX)
  216. help
  217. The Primary-to-Sideband bus is used to access various peripherals
  218. through memory-mapped I/O in a large chunk of PCI space. The space is
  219. segmented into different channels and peripherals are accessed by
  220. device-specific means within those channels. Devices should be added
  221. in the device tree as subnodes of the p2sb.
  222. config TPL_P2SB
  223. bool "Intel Primary-to-Sideband Bus in TPL"
  224. depends on TPL && (X86 || SANDBOX)
  225. help
  226. The Primary-to-Sideband bus is used to access various peripherals
  227. through memory-mapped I/O in a large chunk of PCI space. The space is
  228. segmented into different channels and peripherals are accessed by
  229. device-specific means within those channels. Devices should be added
  230. in the device tree as subnodes of the p2sb.
  231. config PWRSEQ
  232. bool "Enable power-sequencing drivers"
  233. depends on DM
  234. help
  235. Power-sequencing drivers provide support for controlling power for
  236. devices. They are typically referenced by a phandle from another
  237. device. When the device is started up, its power sequence can be
  238. initiated.
  239. config SPL_PWRSEQ
  240. bool "Enable power-sequencing drivers for SPL"
  241. depends on PWRSEQ
  242. help
  243. Power-sequencing drivers provide support for controlling power for
  244. devices. They are typically referenced by a phandle from another
  245. device. When the device is started up, its power sequence can be
  246. initiated.
  247. config PCA9551_LED
  248. bool "Enable PCA9551 LED driver"
  249. help
  250. Enable driver for PCA9551 LED controller. This controller
  251. is connected via I2C. So I2C needs to be enabled.
  252. config PCA9551_I2C_ADDR
  253. hex "I2C address of PCA9551 LED controller"
  254. depends on PCA9551_LED
  255. default 0x60
  256. help
  257. The I2C address of the PCA9551 LED controller.
  258. config STM32MP_FUSE
  259. bool "Enable STM32MP fuse wrapper providing the fuse API"
  260. depends on ARCH_STM32MP && MISC
  261. default y if CMD_FUSE
  262. help
  263. If you say Y here, you will get support for the fuse API (OTP)
  264. for STM32MP architecture.
  265. This API is needed for CMD_FUSE.
  266. config STM32_RCC
  267. bool "Enable RCC driver for the STM32 SoC's family"
  268. depends on (STM32 || ARCH_STM32MP) && MISC
  269. help
  270. Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
  271. block) is responsible of the management of the clock and reset
  272. generation.
  273. This driver is similar to an MFD driver in the Linux kernel.
  274. config TEGRA_CAR
  275. bool "Enable support for the Tegra CAR driver"
  276. depends on TEGRA_NO_BPMP
  277. help
  278. The Tegra CAR (Clock and Reset Controller) is a HW module that
  279. controls almost all clocks and resets in a Tegra SoC.
  280. config TEGRA186_BPMP
  281. bool "Enable support for the Tegra186 BPMP driver"
  282. depends on TEGRA186
  283. help
  284. The Tegra BPMP (Boot and Power Management Processor) is a separate
  285. auxiliary CPU embedded into Tegra to perform power management work,
  286. and controls related features such as clocks, resets, power domains,
  287. PMIC I2C bus, etc. This driver provides the core low-level
  288. communication path by which feature-specific drivers (such as clock)
  289. can make requests to the BPMP. This driver is similar to an MFD
  290. driver in the Linux kernel.
  291. config TWL4030_LED
  292. bool "Enable TWL4030 LED controller"
  293. help
  294. Enable this to add support for the TWL4030 LED controller.
  295. config WINBOND_W83627
  296. bool "Enable Winbond Super I/O driver"
  297. help
  298. If you say Y here, you will get support for the Winbond
  299. W83627 Super I/O driver. This can be used to enable the
  300. legacy UART or other devices in the Winbond Super IO chips
  301. on X86 platforms.
  302. config QFW
  303. bool
  304. help
  305. Hidden option to enable QEMU fw_cfg interface. This will be selected by
  306. either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
  307. config I2C_EEPROM
  308. bool "Enable driver for generic I2C-attached EEPROMs"
  309. depends on MISC
  310. help
  311. Enable a generic driver for EEPROMs attached via I2C.
  312. config SPL_I2C_EEPROM
  313. bool "Enable driver for generic I2C-attached EEPROMs for SPL"
  314. depends on MISC && SPL && SPL_DM
  315. help
  316. This option is an SPL-variant of the I2C_EEPROM option.
  317. See the help of I2C_EEPROM for details.
  318. config ZYNQ_GEM_I2C_MAC_OFFSET
  319. hex "Set the I2C MAC offset"
  320. default 0x0
  321. depends on DM_I2C
  322. help
  323. Set the MAC offset for i2C.
  324. if I2C_EEPROM
  325. config SYS_I2C_EEPROM_ADDR
  326. hex "Chip address of the EEPROM device"
  327. default 0
  328. config SYS_I2C_EEPROM_BUS
  329. int "I2C bus of the EEPROM device."
  330. default 0
  331. config SYS_EEPROM_SIZE
  332. int "Size in bytes of the EEPROM device"
  333. default 256
  334. config SYS_EEPROM_PAGE_WRITE_BITS
  335. int "Number of bits used to address bytes in a single page"
  336. default 0
  337. help
  338. The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
  339. A 64 byte page, for example would require six bits.
  340. config SYS_EEPROM_PAGE_WRITE_DELAY_MS
  341. int "Number of milliseconds to delay between page writes"
  342. default 0
  343. config SYS_I2C_EEPROM_ADDR_LEN
  344. int "Length in bytes of the EEPROM memory array address"
  345. default 1
  346. help
  347. Note: This is NOT the chip address length!
  348. config SYS_I2C_EEPROM_ADDR_OVERFLOW
  349. hex "EEPROM Address Overflow"
  350. default 0
  351. help
  352. EEPROM chips that implement "address overflow" are ones
  353. like Catalyst 24WC04/08/16 which has 9/10/11 bits of
  354. address and the extra bits end up in the "chip address" bit
  355. slots. This makes a 24WC08 (1Kbyte) chip look like four 256
  356. byte chips.
  357. endif
  358. config GDSYS_RXAUI_CTRL
  359. bool "Enable gdsys RXAUI control driver"
  360. depends on MISC
  361. help
  362. Support gdsys FPGA's RXAUI control.
  363. config GDSYS_IOEP
  364. bool "Enable gdsys IOEP driver"
  365. depends on MISC
  366. help
  367. Support gdsys FPGA's IO endpoint driver.
  368. config MPC83XX_SERDES
  369. bool "Enable MPC83xx serdes driver"
  370. depends on MISC
  371. help
  372. Support for serdes found on MPC83xx SoCs.
  373. config FS_LOADER
  374. bool "Enable loader driver for file system"
  375. help
  376. This is file system generic loader which can be used to load
  377. the file image from the storage into target such as memory.
  378. The consumer driver would then use this loader to program whatever,
  379. ie. the FPGA device.
  380. config GDSYS_SOC
  381. bool "Enable gdsys SOC driver"
  382. depends on MISC
  383. help
  384. Support for gdsys IHS SOC, a simple bus associated with each gdsys
  385. IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
  386. register maps are contained within the FPGA's register map.
  387. config IHS_FPGA
  388. bool "Enable IHS FPGA driver"
  389. depends on MISC
  390. help
  391. Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
  392. gdsys devices, which supply the majority of the functionality offered
  393. by the devices. This driver supports both CON and CPU variants of the
  394. devices, depending on the device tree entry.
  395. config MICROCHIP_FLEXCOM
  396. bool "Enable Microchip Flexcom driver"
  397. depends on MISC
  398. help
  399. The Atmel Flexcom is just a wrapper which embeds a SPI controller,
  400. an I2C controller and an USART.
  401. Only one function can be used at a time and is chosen at boot time
  402. according to the device tree.
  403. config K3_AVS0
  404. depends on ARCH_K3 && SPL_DM_REGULATOR
  405. bool "AVS class 0 support for K3 devices"
  406. help
  407. K3 devices have the optimized voltage values for the main voltage
  408. domains stored in efuse within the VTM IP. This driver reads the
  409. optimized voltage from the efuse, so that it can be programmed
  410. to the PMIC on board.
  411. endmenu