Config.in.arm 26 KB

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  1. # arm cpu features
  2. config BR2_ARM_CPU_HAS_NEON
  3. bool
  4. # for some cores, NEON support is optional
  5. config BR2_ARM_CPU_MAYBE_HAS_NEON
  6. bool
  7. # For some cores, the FPU is optional
  8. config BR2_ARM_CPU_MAYBE_HAS_FPU
  9. bool
  10. config BR2_ARM_CPU_HAS_FPU
  11. bool
  12. # for some cores, VFPv2 is optional
  13. config BR2_ARM_CPU_MAYBE_HAS_VFPV2
  14. bool
  15. select BR2_ARM_CPU_MAYBE_HAS_FPU
  16. config BR2_ARM_CPU_HAS_VFPV2
  17. bool
  18. select BR2_ARM_CPU_HAS_FPU
  19. # for some cores, VFPv3 is optional
  20. config BR2_ARM_CPU_MAYBE_HAS_VFPV3
  21. bool
  22. select BR2_ARM_CPU_MAYBE_HAS_VFPV2
  23. config BR2_ARM_CPU_HAS_VFPV3
  24. bool
  25. select BR2_ARM_CPU_HAS_VFPV2
  26. # for some cores, VFPv4 is optional
  27. config BR2_ARM_CPU_MAYBE_HAS_VFPV4
  28. bool
  29. select BR2_ARM_CPU_MAYBE_HAS_VFPV3
  30. config BR2_ARM_CPU_HAS_VFPV4
  31. bool
  32. select BR2_ARM_CPU_HAS_VFPV3
  33. # FPv4 is always optional
  34. config BR2_ARM_CPU_MAYBE_HAS_FPV4
  35. bool
  36. select BR2_ARM_CPU_MAYBE_HAS_FPU
  37. config BR2_ARM_CPU_HAS_FPV4
  38. bool
  39. select BR2_ARM_CPU_HAS_FPU
  40. # FPv5 is always optional
  41. config BR2_ARM_CPU_MAYBE_HAS_FPV5
  42. bool
  43. select BR2_ARM_CPU_MAYBE_HAS_FPV4
  44. config BR2_ARM_CPU_HAS_FPV5
  45. bool
  46. select BR2_ARM_CPU_HAS_FPV4
  47. config BR2_ARM_CPU_HAS_FP_ARMV8
  48. bool
  49. select BR2_ARM_CPU_HAS_VFPV4
  50. config BR2_ARM_CPU_HAS_ARM
  51. bool
  52. config BR2_ARM_CPU_HAS_THUMB
  53. bool
  54. config BR2_ARM_CPU_HAS_THUMB2
  55. bool
  56. config BR2_ARM_CPU_ARMV4
  57. bool
  58. config BR2_ARM_CPU_ARMV5
  59. bool
  60. config BR2_ARM_CPU_ARMV6
  61. bool
  62. config BR2_ARM_CPU_ARMV7A
  63. bool
  64. config BR2_ARM_CPU_ARMV7M
  65. bool
  66. config BR2_ARM_CPU_ARMV8A
  67. bool
  68. choice
  69. prompt "Target Architecture Variant"
  70. default BR2_cortex_a53 if BR2_ARCH_IS_64
  71. default BR2_arm926t
  72. help
  73. Specific CPU variant to use
  74. if !BR2_ARCH_IS_64
  75. comment "armv4 cores"
  76. config BR2_arm920t
  77. bool "arm920t"
  78. select BR2_ARM_CPU_HAS_ARM
  79. select BR2_ARM_CPU_HAS_THUMB
  80. select BR2_ARM_CPU_ARMV4
  81. select BR2_ARCH_HAS_MMU_OPTIONAL
  82. config BR2_arm922t
  83. bool "arm922t"
  84. select BR2_ARM_CPU_HAS_ARM
  85. select BR2_ARM_CPU_HAS_THUMB
  86. select BR2_ARM_CPU_ARMV4
  87. select BR2_ARCH_HAS_MMU_OPTIONAL
  88. config BR2_fa526
  89. bool "fa526/626"
  90. select BR2_ARM_CPU_HAS_ARM
  91. select BR2_ARM_CPU_ARMV4
  92. select BR2_ARCH_HAS_MMU_OPTIONAL
  93. config BR2_strongarm
  94. bool "strongarm sa110/sa1100"
  95. select BR2_ARM_CPU_HAS_ARM
  96. select BR2_ARM_CPU_ARMV4
  97. select BR2_ARCH_HAS_MMU_OPTIONAL
  98. comment "armv5 cores"
  99. config BR2_arm926t
  100. bool "arm926t"
  101. select BR2_ARM_CPU_HAS_ARM
  102. select BR2_ARM_CPU_MAYBE_HAS_VFPV2
  103. select BR2_ARM_CPU_HAS_THUMB
  104. select BR2_ARM_CPU_ARMV5
  105. select BR2_ARCH_HAS_MMU_OPTIONAL
  106. config BR2_iwmmxt
  107. bool "iwmmxt"
  108. select BR2_ARM_CPU_HAS_ARM
  109. select BR2_ARM_CPU_ARMV5
  110. select BR2_ARCH_HAS_MMU_OPTIONAL
  111. config BR2_xscale
  112. bool "xscale"
  113. select BR2_ARM_CPU_HAS_ARM
  114. select BR2_ARM_CPU_HAS_THUMB
  115. select BR2_ARM_CPU_ARMV5
  116. select BR2_ARCH_HAS_MMU_OPTIONAL
  117. comment "armv6 cores"
  118. config BR2_arm1136j_s
  119. bool "arm1136j-s"
  120. select BR2_ARM_CPU_HAS_ARM
  121. select BR2_ARM_CPU_HAS_THUMB
  122. select BR2_ARM_CPU_ARMV6
  123. select BR2_ARCH_HAS_MMU_OPTIONAL
  124. config BR2_arm1136jf_s
  125. bool "arm1136jf-s"
  126. select BR2_ARM_CPU_HAS_ARM
  127. select BR2_ARM_CPU_HAS_VFPV2
  128. select BR2_ARM_CPU_HAS_THUMB
  129. select BR2_ARM_CPU_ARMV6
  130. select BR2_ARCH_HAS_MMU_OPTIONAL
  131. config BR2_arm1176jz_s
  132. bool "arm1176jz-s"
  133. select BR2_ARM_CPU_HAS_ARM
  134. select BR2_ARM_CPU_HAS_THUMB
  135. select BR2_ARM_CPU_ARMV6
  136. select BR2_ARCH_HAS_MMU_OPTIONAL
  137. config BR2_arm1176jzf_s
  138. bool "arm1176jzf-s"
  139. select BR2_ARM_CPU_HAS_ARM
  140. select BR2_ARM_CPU_HAS_VFPV2
  141. select BR2_ARM_CPU_HAS_THUMB
  142. select BR2_ARM_CPU_ARMV6
  143. select BR2_ARCH_HAS_MMU_OPTIONAL
  144. config BR2_arm11mpcore
  145. bool "mpcore"
  146. select BR2_ARM_CPU_HAS_ARM
  147. select BR2_ARM_CPU_MAYBE_HAS_VFPV2
  148. select BR2_ARM_CPU_HAS_THUMB
  149. select BR2_ARM_CPU_ARMV6
  150. select BR2_ARCH_HAS_MMU_OPTIONAL
  151. comment "armv7a cores"
  152. config BR2_cortex_a5
  153. bool "cortex-A5"
  154. select BR2_ARM_CPU_HAS_ARM
  155. select BR2_ARM_CPU_MAYBE_HAS_NEON
  156. select BR2_ARM_CPU_MAYBE_HAS_VFPV4
  157. select BR2_ARM_CPU_HAS_THUMB2
  158. select BR2_ARM_CPU_ARMV7A
  159. select BR2_ARCH_HAS_MMU_OPTIONAL
  160. config BR2_cortex_a7
  161. bool "cortex-A7"
  162. select BR2_ARM_CPU_HAS_ARM
  163. select BR2_ARM_CPU_HAS_NEON
  164. select BR2_ARM_CPU_HAS_VFPV4
  165. select BR2_ARM_CPU_HAS_THUMB2
  166. select BR2_ARM_CPU_ARMV7A
  167. select BR2_ARCH_HAS_MMU_OPTIONAL
  168. config BR2_cortex_a8
  169. bool "cortex-A8"
  170. select BR2_ARM_CPU_HAS_ARM
  171. select BR2_ARM_CPU_HAS_NEON
  172. select BR2_ARM_CPU_HAS_VFPV3
  173. select BR2_ARM_CPU_HAS_THUMB2
  174. select BR2_ARM_CPU_ARMV7A
  175. select BR2_ARCH_HAS_MMU_OPTIONAL
  176. config BR2_cortex_a9
  177. bool "cortex-A9"
  178. select BR2_ARM_CPU_HAS_ARM
  179. select BR2_ARM_CPU_MAYBE_HAS_NEON
  180. select BR2_ARM_CPU_MAYBE_HAS_VFPV3
  181. select BR2_ARM_CPU_HAS_THUMB2
  182. select BR2_ARM_CPU_ARMV7A
  183. select BR2_ARCH_HAS_MMU_OPTIONAL
  184. config BR2_cortex_a12
  185. bool "cortex-A12"
  186. select BR2_ARM_CPU_HAS_ARM
  187. select BR2_ARM_CPU_HAS_NEON
  188. select BR2_ARM_CPU_HAS_VFPV4
  189. select BR2_ARM_CPU_HAS_THUMB2
  190. select BR2_ARM_CPU_ARMV7A
  191. select BR2_ARCH_HAS_MMU_OPTIONAL
  192. config BR2_cortex_a15
  193. bool "cortex-A15"
  194. select BR2_ARM_CPU_HAS_ARM
  195. select BR2_ARM_CPU_HAS_NEON
  196. select BR2_ARM_CPU_HAS_VFPV4
  197. select BR2_ARM_CPU_HAS_THUMB2
  198. select BR2_ARM_CPU_ARMV7A
  199. select BR2_ARCH_HAS_MMU_OPTIONAL
  200. config BR2_cortex_a15_a7
  201. bool "cortex-A15/A7 big.LITTLE"
  202. select BR2_ARM_CPU_HAS_ARM
  203. select BR2_ARM_CPU_HAS_NEON
  204. select BR2_ARM_CPU_HAS_VFPV4
  205. select BR2_ARM_CPU_HAS_THUMB2
  206. select BR2_ARM_CPU_ARMV7A
  207. select BR2_ARCH_HAS_MMU_OPTIONAL
  208. select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
  209. config BR2_cortex_a17
  210. bool "cortex-A17"
  211. select BR2_ARM_CPU_HAS_ARM
  212. select BR2_ARM_CPU_HAS_NEON
  213. select BR2_ARM_CPU_HAS_VFPV4
  214. select BR2_ARM_CPU_HAS_THUMB2
  215. select BR2_ARM_CPU_ARMV7A
  216. select BR2_ARCH_HAS_MMU_OPTIONAL
  217. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  218. config BR2_cortex_a17_a7
  219. bool "cortex-A17/A7 big.LITTLE"
  220. select BR2_ARM_CPU_HAS_ARM
  221. select BR2_ARM_CPU_HAS_NEON
  222. select BR2_ARM_CPU_HAS_VFPV4
  223. select BR2_ARM_CPU_HAS_THUMB2
  224. select BR2_ARM_CPU_ARMV7A
  225. select BR2_ARCH_HAS_MMU_OPTIONAL
  226. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  227. config BR2_pj4
  228. bool "pj4"
  229. select BR2_ARM_CPU_HAS_ARM
  230. select BR2_ARM_CPU_HAS_VFPV3
  231. select BR2_ARM_CPU_ARMV7A
  232. select BR2_ARCH_HAS_MMU_OPTIONAL
  233. comment "armv7m cores"
  234. config BR2_cortex_m3
  235. bool "cortex-M3"
  236. select BR2_ARM_CPU_HAS_THUMB2
  237. select BR2_ARM_CPU_ARMV7M
  238. config BR2_cortex_m4
  239. bool "cortex-M4"
  240. select BR2_ARM_CPU_HAS_THUMB2
  241. select BR2_ARM_CPU_MAYBE_HAS_FPV4
  242. select BR2_ARM_CPU_ARMV7M
  243. config BR2_cortex_m7
  244. bool "cortex-M7"
  245. select BR2_ARM_CPU_HAS_THUMB2
  246. select BR2_ARM_CPU_MAYBE_HAS_FPV5
  247. select BR2_ARM_CPU_ARMV7M
  248. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  249. endif # !BR2_ARCH_IS_64
  250. comment "armv8 cores"
  251. config BR2_cortex_a32
  252. bool "cortex-A32"
  253. depends on !BR2_ARCH_IS_64
  254. select BR2_ARM_CPU_HAS_ARM
  255. select BR2_ARM_CPU_HAS_NEON
  256. select BR2_ARM_CPU_HAS_THUMB2
  257. select BR2_ARM_CPU_HAS_FP_ARMV8
  258. select BR2_ARM_CPU_ARMV8A
  259. select BR2_ARCH_HAS_MMU_OPTIONAL
  260. select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  261. config BR2_cortex_a35
  262. bool "cortex-A35"
  263. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  264. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  265. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  266. select BR2_ARM_CPU_HAS_FP_ARMV8
  267. select BR2_ARM_CPU_ARMV8A
  268. select BR2_ARCH_HAS_MMU_OPTIONAL
  269. select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  270. config BR2_cortex_a53
  271. bool "cortex-A53"
  272. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  273. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  274. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  275. select BR2_ARM_CPU_HAS_FP_ARMV8
  276. select BR2_ARM_CPU_ARMV8A
  277. select BR2_ARCH_HAS_MMU_OPTIONAL
  278. config BR2_cortex_a57
  279. bool "cortex-A57"
  280. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  281. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  282. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  283. select BR2_ARM_CPU_HAS_FP_ARMV8
  284. select BR2_ARM_CPU_ARMV8A
  285. select BR2_ARCH_HAS_MMU_OPTIONAL
  286. config BR2_cortex_a57_a53
  287. bool "cortex-A57/A53 big.LITTLE"
  288. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  289. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  290. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  291. select BR2_ARM_CPU_HAS_FP_ARMV8
  292. select BR2_ARM_CPU_ARMV8A
  293. select BR2_ARCH_HAS_MMU_OPTIONAL
  294. select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  295. config BR2_cortex_a72
  296. bool "cortex-A72"
  297. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  298. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  299. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  300. select BR2_ARM_CPU_HAS_FP_ARMV8
  301. select BR2_ARM_CPU_ARMV8A
  302. select BR2_ARCH_HAS_MMU_OPTIONAL
  303. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  304. config BR2_cortex_a72_a53
  305. bool "cortex-A72/A53 big.LITTLE"
  306. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  307. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  308. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  309. select BR2_ARM_CPU_HAS_FP_ARMV8
  310. select BR2_ARM_CPU_ARMV8A
  311. select BR2_ARCH_HAS_MMU_OPTIONAL
  312. select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  313. config BR2_cortex_a73
  314. bool "cortex-A73"
  315. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  316. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  317. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  318. select BR2_ARM_CPU_HAS_FP_ARMV8
  319. select BR2_ARM_CPU_ARMV8A
  320. select BR2_ARCH_HAS_MMU_OPTIONAL
  321. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  322. config BR2_cortex_a73_a35
  323. bool "cortex-A73/A35 big.LITTLE"
  324. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  325. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  326. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  327. select BR2_ARM_CPU_HAS_FP_ARMV8
  328. select BR2_ARM_CPU_ARMV8A
  329. select BR2_ARCH_HAS_MMU_OPTIONAL
  330. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  331. config BR2_cortex_a73_a53
  332. bool "cortex-A73/A53 big.LITTLE"
  333. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  334. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  335. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  336. select BR2_ARM_CPU_HAS_FP_ARMV8
  337. select BR2_ARM_CPU_ARMV8A
  338. select BR2_ARCH_HAS_MMU_OPTIONAL
  339. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  340. config BR2_exynos_m1
  341. bool "exynos-m1"
  342. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  343. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  344. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  345. select BR2_ARM_CPU_HAS_FP_ARMV8
  346. select BR2_ARM_CPU_ARMV8A
  347. select BR2_ARCH_HAS_MMU_OPTIONAL
  348. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  349. if BR2_ARCH_IS_64
  350. config BR2_falkor
  351. bool "falkor"
  352. select BR2_ARM_CPU_HAS_FP_ARMV8
  353. select BR2_ARM_CPU_ARMV8A
  354. select BR2_ARCH_HAS_MMU_OPTIONAL
  355. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  356. config BR2_qdf24xx
  357. bool "qdf24xx"
  358. select BR2_ARM_CPU_HAS_FP_ARMV8
  359. select BR2_ARM_CPU_ARMV8A
  360. select BR2_ARCH_HAS_MMU_OPTIONAL
  361. select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  362. config BR2_thunderx
  363. bool "thunderx"
  364. select BR2_ARM_CPU_HAS_FP_ARMV8
  365. select BR2_ARM_CPU_ARMV8A
  366. select BR2_ARCH_HAS_MMU_OPTIONAL
  367. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  368. config BR2_thunderxt81
  369. bool "thunderxt81"
  370. select BR2_ARM_CPU_HAS_FP_ARMV8
  371. select BR2_ARM_CPU_ARMV8A
  372. select BR2_ARCH_HAS_MMU_OPTIONAL
  373. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  374. config BR2_thunderxt83
  375. bool "thunderxt83"
  376. select BR2_ARM_CPU_HAS_FP_ARMV8
  377. select BR2_ARM_CPU_ARMV8A
  378. select BR2_ARCH_HAS_MMU_OPTIONAL
  379. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  380. config BR2_thunderxt88
  381. bool "thunderxt88"
  382. select BR2_ARM_CPU_HAS_FP_ARMV8
  383. select BR2_ARM_CPU_ARMV8A
  384. select BR2_ARCH_HAS_MMU_OPTIONAL
  385. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  386. config BR2_thunderxt88p1
  387. bool "thunderxt88p1"
  388. select BR2_ARM_CPU_HAS_FP_ARMV8
  389. select BR2_ARM_CPU_ARMV8A
  390. select BR2_ARCH_HAS_MMU_OPTIONAL
  391. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  392. endif # BR2_ARCH_IS_64
  393. config BR2_xgene1
  394. bool "xgene1"
  395. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  396. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  397. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  398. select BR2_ARM_CPU_HAS_FP_ARMV8
  399. select BR2_ARM_CPU_ARMV8A
  400. select BR2_ARCH_HAS_MMU_OPTIONAL
  401. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  402. if BR2_ARCH_IS_64
  403. comment "armv8.1a cores"
  404. config BR2_thunderx2t99
  405. bool "thunderx2t99"
  406. select BR2_ARM_CPU_HAS_FP_ARMV8
  407. select BR2_ARM_CPU_ARMV8A
  408. select BR2_ARCH_HAS_MMU_OPTIONAL
  409. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  410. config BR2_thunderx2t99p1
  411. bool "thunderx2t99p1"
  412. select BR2_ARM_CPU_HAS_FP_ARMV8
  413. select BR2_ARM_CPU_ARMV8A
  414. select BR2_ARCH_HAS_MMU_OPTIONAL
  415. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  416. config BR2_vulcan
  417. bool "vulcan"
  418. select BR2_ARM_CPU_HAS_FP_ARMV8
  419. select BR2_ARM_CPU_ARMV8A
  420. select BR2_ARCH_HAS_MMU_OPTIONAL
  421. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  422. endif # BR2_ARCH_IS_64
  423. if BR2_ARCH_IS_64
  424. comment "armv8.2a cores"
  425. config BR2_cortex_a55
  426. bool "cortex-A55"
  427. select BR2_ARM_CPU_HAS_FP_ARMV8
  428. select BR2_ARM_CPU_ARMV8A
  429. select BR2_ARCH_HAS_MMU_OPTIONAL
  430. select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
  431. config BR2_cortex_a75
  432. bool "cortex-A75"
  433. select BR2_ARM_CPU_HAS_FP_ARMV8
  434. select BR2_ARM_CPU_ARMV8A
  435. select BR2_ARCH_HAS_MMU_OPTIONAL
  436. select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
  437. config BR2_cortex_a75_a55
  438. bool "cortex-A75/A55 big.LITTLE"
  439. select BR2_ARM_CPU_HAS_FP_ARMV8
  440. select BR2_ARM_CPU_ARMV8A
  441. select BR2_ARCH_HAS_MMU_OPTIONAL
  442. select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
  443. endif # BR2_ARCH_IS_64
  444. if BR2_ARCH_IS_64
  445. comment "armv8.3a cores"
  446. config BR2_saphira
  447. bool "saphira"
  448. select BR2_ARM_CPU_HAS_FP_ARMV8
  449. select BR2_ARM_CPU_ARMV8A
  450. select BR2_ARCH_HAS_MMU_OPTIONAL
  451. select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
  452. endif # BR2_ARCH_IS_64
  453. endchoice
  454. config BR2_ARM_ENABLE_NEON
  455. bool "Enable NEON SIMD extension support"
  456. depends on BR2_ARM_CPU_MAYBE_HAS_NEON
  457. select BR2_ARM_CPU_HAS_NEON
  458. help
  459. For some CPU cores, the NEON SIMD extension is optional.
  460. Select this option if you are certain your particular
  461. implementation has NEON support and you want to use it.
  462. config BR2_ARM_ENABLE_VFP
  463. bool "Enable VFP extension support"
  464. depends on BR2_ARM_CPU_MAYBE_HAS_FPU
  465. select BR2_ARM_CPU_HAS_FPV5 if BR2_ARM_CPU_MAYBE_HAS_FPV5
  466. select BR2_ARM_CPU_HAS_FPV4 if BR2_ARM_CPU_MAYBE_HAS_FPV4
  467. select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4
  468. select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3
  469. select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2
  470. help
  471. For some CPU cores, the VFP extension is optional. Select
  472. this option if you are certain your particular
  473. implementation has VFP support and you want to use it.
  474. choice
  475. prompt "Target ABI"
  476. default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_FPU
  477. default BR2_ARM_EABI
  478. depends on BR2_arm || BR2_armeb
  479. help
  480. Application Binary Interface to use. The Application Binary
  481. Interface describes the calling conventions (how arguments
  482. are passed to functions, how the return value is passed, how
  483. system calls are made, etc.).
  484. config BR2_ARM_EABI
  485. bool "EABI"
  486. help
  487. The EABI is currently the standard ARM ABI, which is used in
  488. most projects. It supports both the 'soft' floating point
  489. model (in which floating point instructions are emulated in
  490. software) and the 'softfp' floating point model (in which
  491. floating point instructions are executed using an hardware
  492. floating point unit, but floating point arguments to
  493. functions are passed in integer registers).
  494. The 'softfp' floating point model is link-compatible with
  495. the 'soft' floating point model, i.e you can link a library
  496. built 'soft' with some other code built 'softfp'.
  497. However, passing the floating point arguments in integer
  498. registers is a bit inefficient, so if your ARM processor has
  499. a floating point unit, and you don't have pre-compiled
  500. 'soft' or 'softfp' code, using the EABIhf ABI will provide
  501. better floating point performances.
  502. If your processor does not have a floating point unit, then
  503. you must use this ABI.
  504. config BR2_ARM_EABIHF
  505. bool "EABIhf"
  506. depends on BR2_ARM_CPU_HAS_FPU
  507. help
  508. The EABIhf is an extension of EABI which supports the 'hard'
  509. floating point model. This model uses the floating point
  510. unit to execute floating point instructions, and passes
  511. floating point arguments in floating point registers.
  512. It is more efficient than EABI for floating point related
  513. workload. However, it does not allow to link against code
  514. that has been pre-built for the 'soft' or 'softfp' floating
  515. point models.
  516. If your processor has a floating point unit, and you don't
  517. depend on existing pre-compiled code, this option is most
  518. likely the best choice.
  519. endchoice
  520. choice
  521. prompt "Floating point strategy"
  522. default BR2_ARM_FPU_FP_ARMV8 if BR2_ARM_CPU_HAS_FP_ARMV8
  523. default BR2_ARM_FPU_FPV5D16 if BR2_ARM_CPU_HAS_FPV5
  524. default BR2_ARM_FPU_FPV4D16 if BR2_ARM_CPU_HAS_FPV4
  525. default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
  526. default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
  527. default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
  528. default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_FPU
  529. config BR2_ARM_SOFT_FLOAT
  530. bool "Soft float"
  531. depends on BR2_ARM_EABI
  532. select BR2_SOFT_FLOAT
  533. help
  534. This option allows to use software emulated floating
  535. point. It should be used for ARM cores that do not include a
  536. Vector Floating Point unit, such as ARMv5 cores (ARM926 for
  537. example) or certain ARMv6 cores.
  538. config BR2_ARM_FPU_VFPV2
  539. bool "VFPv2"
  540. depends on BR2_ARM_CPU_HAS_VFPV2
  541. help
  542. This option allows to use the VFPv2 floating point unit, as
  543. available in some ARMv5 processors (ARM926EJ-S) and some
  544. ARMv6 processors (ARM1136JF-S, ARM1176JZF-S and ARM11
  545. MPCore).
  546. Note that this option is also safe to use for newer cores
  547. such as Cortex-A, because the VFPv3 and VFPv4 units are
  548. backward compatible with VFPv2.
  549. config BR2_ARM_FPU_VFPV3
  550. bool "VFPv3"
  551. depends on BR2_ARM_CPU_HAS_VFPV3
  552. help
  553. This option allows to use the VFPv3 floating point unit, as
  554. available in some ARMv7 processors (Cortex-A{8, 9}). This
  555. option requires a VFPv3 unit that has 32 double-precision
  556. registers, which is not necessarily the case in all SOCs
  557. based on Cortex-A{8, 9}. If you're unsure, use VFPv3-D16
  558. instead, which is guaranteed to work on all Cortex-A{8, 9}.
  559. Note that this option is also safe to use for newer cores
  560. that have a VFPv4 unit, because VFPv4 is backward compatible
  561. with VFPv3. They must of course also have 32
  562. double-precision registers.
  563. config BR2_ARM_FPU_VFPV3D16
  564. bool "VFPv3-D16"
  565. depends on BR2_ARM_CPU_HAS_VFPV3
  566. help
  567. This option allows to use the VFPv3 floating point unit, as
  568. available in some ARMv7 processors (Cortex-A{8, 9}). This
  569. option requires a VFPv3 unit that has 16 double-precision
  570. registers, which is generally the case in all SOCs based on
  571. Cortex-A{8, 9}, even though VFPv3 is technically optional on
  572. Cortex-A9. This is the safest option for those cores.
  573. Note that this option is also safe to use for newer cores
  574. such that have a VFPv4 unit, because the VFPv4 is backward
  575. compatible with VFPv3.
  576. config BR2_ARM_FPU_VFPV4
  577. bool "VFPv4"
  578. depends on BR2_ARM_CPU_HAS_VFPV4
  579. help
  580. This option allows to use the VFPv4 floating point unit, as
  581. available in some ARMv7 processors (Cortex-A{5, 7, 12,
  582. 15}). This option requires a VFPv4 unit that has 32
  583. double-precision registers, which is not necessarily the
  584. case in all SOCs based on Cortex-A{5, 7, 12, 15}. If you're
  585. unsure, you should probably use VFPv4-D16 instead.
  586. Note that if you want binary code that works on all ARMv7
  587. cores, including the earlier Cortex-A{8, 9}, you should
  588. instead select VFPv3.
  589. config BR2_ARM_FPU_VFPV4D16
  590. bool "VFPv4-D16"
  591. depends on BR2_ARM_CPU_HAS_VFPV4
  592. help
  593. This option allows to use the VFPv4 floating point unit, as
  594. available in some ARMv7 processors (Cortex-A{5, 7, 12,
  595. 15}). This option requires a VFPv4 unit that has 16
  596. double-precision registers, which is always available on
  597. Cortex-A12 and Cortex-A15, but optional on Cortex-A5 and
  598. Cortex-A7.
  599. Note that if you want binary code that works on all ARMv7
  600. cores, including the earlier Cortex-A{8, 9}, you should
  601. instead select VFPv3-D16.
  602. config BR2_ARM_FPU_NEON
  603. bool "NEON"
  604. depends on BR2_ARM_CPU_HAS_NEON
  605. help
  606. This option allows to use the NEON SIMD unit, as available
  607. in some ARMv7 processors, as a floating-point unit. It
  608. should however be noted that using NEON for floating point
  609. operations doesn't provide a complete compatibility with the
  610. IEEE 754.
  611. config BR2_ARM_FPU_NEON_VFPV4
  612. bool "NEON/VFPv4"
  613. depends on BR2_ARM_CPU_HAS_VFPV4
  614. depends on BR2_ARM_CPU_HAS_NEON
  615. help
  616. This option allows to use both the VFPv4 and the NEON SIMD
  617. units for floating point operations. Note that some ARMv7
  618. cores do not necessarily have VFPv4 and/or NEON support, for
  619. example on Cortex-A5 and Cortex-A7, support for VFPv4 and
  620. NEON is optional.
  621. config BR2_ARM_FPU_FPV4D16
  622. bool "FPv4-D16"
  623. depends on BR2_ARM_CPU_HAS_FPV4
  624. help
  625. This option allows to use the FPv4-SP (single precision)
  626. floating point unit, as available in some ARMv7m processors
  627. (Cortex-M4).
  628. config BR2_ARM_FPU_FPV5D16
  629. bool "FPv5-D16"
  630. depends on BR2_ARM_CPU_HAS_FPV5
  631. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  632. help
  633. This option allows to use the FPv5-SP (single precision)
  634. floating point unit, as available in some ARMv7m processors
  635. (Cortex-M7).
  636. Note that if you want binary code that works on the earlier
  637. Cortex-M4, you should instead select FPv4-D16.
  638. config BR2_ARM_FPU_FPV5DPD16
  639. bool "FPv5-DP-D16"
  640. depends on BR2_ARM_CPU_HAS_FPV5
  641. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  642. help
  643. This option allows to use the FPv5-DP (double precision)
  644. floating point unit, as available in some ARMv7m processors
  645. (Cortex-M7).
  646. Note that if you want binary code that works on the earlier
  647. Cortex-M4, you should instead select FPv4-D16.
  648. config BR2_ARM_FPU_FP_ARMV8
  649. bool "FP-ARMv8"
  650. depends on BR2_ARM_CPU_HAS_FP_ARMV8
  651. help
  652. This option allows to use the ARMv8 floating point unit.
  653. config BR2_ARM_FPU_NEON_FP_ARMV8
  654. bool "NEON/FP-ARMv8"
  655. depends on BR2_ARM_CPU_HAS_FP_ARMV8
  656. depends on BR2_ARM_CPU_HAS_NEON
  657. help
  658. This option allows to use both the ARMv8 floating point unit
  659. and the NEON SIMD unit for floating point operations.
  660. endchoice
  661. choice
  662. prompt "ARM instruction set"
  663. depends on BR2_arm || BR2_armeb
  664. config BR2_ARM_INSTRUCTIONS_ARM
  665. bool "ARM"
  666. depends on BR2_ARM_CPU_HAS_ARM
  667. help
  668. This option instructs the compiler to generate regular ARM
  669. instructions, that are all 32 bits wide.
  670. config BR2_ARM_INSTRUCTIONS_THUMB
  671. bool "Thumb"
  672. depends on BR2_ARM_CPU_HAS_THUMB
  673. # Thumb-1 and VFP are not compatible
  674. depends on BR2_ARM_SOFT_FLOAT
  675. help
  676. This option instructions the compiler to generate Thumb
  677. instructions, which allows to mix 16 bits instructions and
  678. 32 bits instructions. This generally provides a much smaller
  679. compiled binary size.
  680. comment "Thumb1 is not compatible with VFP"
  681. depends on BR2_ARM_CPU_HAS_THUMB
  682. depends on !BR2_ARM_SOFT_FLOAT
  683. config BR2_ARM_INSTRUCTIONS_THUMB2
  684. bool "Thumb2"
  685. depends on BR2_ARM_CPU_HAS_THUMB2
  686. help
  687. This option instructions the compiler to generate Thumb2
  688. instructions, which allows to mix 16 bits instructions and
  689. 32 bits instructions. This generally provides a much smaller
  690. compiled binary size.
  691. endchoice
  692. config BR2_ARCH
  693. default "arm" if BR2_arm
  694. default "armeb" if BR2_armeb
  695. default "aarch64" if BR2_aarch64
  696. default "aarch64_be" if BR2_aarch64_be
  697. config BR2_ENDIAN
  698. default "LITTLE" if (BR2_arm || BR2_aarch64)
  699. default "BIG" if (BR2_armeb || BR2_aarch64_be)
  700. config BR2_GCC_TARGET_CPU
  701. # armv4
  702. default "arm920t" if BR2_arm920t
  703. default "arm922t" if BR2_arm922t
  704. default "fa526" if BR2_fa526
  705. default "strongarm" if BR2_strongarm
  706. # armv5
  707. default "arm926ej-s" if BR2_arm926t
  708. default "iwmmxt" if BR2_iwmmxt
  709. default "xscale" if BR2_xscale
  710. # armv6
  711. default "arm1136j-s" if BR2_arm1136j_s
  712. default "arm1136jf-s" if BR2_arm1136jf_s
  713. default "arm1176jz-s" if BR2_arm1176jz_s
  714. default "arm1176jzf-s" if BR2_arm1176jzf_s
  715. default "mpcore" if BR2_arm11mpcore && BR2_ARM_CPU_HAS_VFPV2
  716. default "mpcorenovfp" if BR2_arm11mpcore
  717. # armv7a
  718. default "cortex-a5" if BR2_cortex_a5
  719. default "cortex-a7" if BR2_cortex_a7
  720. default "cortex-a8" if BR2_cortex_a8
  721. default "cortex-a9" if BR2_cortex_a9
  722. default "cortex-a12" if BR2_cortex_a12
  723. default "cortex-a15" if BR2_cortex_a15
  724. default "cortex-a15.cortex-a7" if BR2_cortex_a15_a7
  725. default "cortex-a17" if BR2_cortex_a17
  726. default "cortex-a17.cortex-a7" if BR2_cortex_a17_a7
  727. default "marvell-pj4" if BR2_pj4
  728. # armv7m
  729. default "cortex-m3" if BR2_cortex_m3
  730. default "cortex-m4" if BR2_cortex_m4
  731. default "cortex-m7" if BR2_cortex_m7
  732. # armv8a
  733. default "cortex-a32" if BR2_cortex_a32
  734. default "cortex-a35" if BR2_cortex_a35
  735. default "cortex-a53" if BR2_cortex_a53
  736. default "cortex-a57" if BR2_cortex_a57
  737. default "cortex-a57.cortex-a53" if BR2_cortex_a57_a53
  738. default "cortex-a72" if BR2_cortex_a72
  739. default "cortex-a72.cortex-a53" if BR2_cortex_a72_a53
  740. default "cortex-a73" if BR2_cortex_a73
  741. default "cortex-a73.cortex-a35" if BR2_cortex_a73_a35
  742. default "cortex-a73.cortex-a53" if BR2_cortex_a73_a53
  743. default "exynos-m1" if BR2_exynos_m1
  744. default "falkor" if BR2_falkor
  745. default "qdf24xx" if BR2_qdf24xx
  746. default "thunderx" if BR2_thunderx
  747. default "thunderxt81" if BR2_thunderxt81
  748. default "thunderxt83" if BR2_thunderxt83
  749. default "thunderxt88" if BR2_thunderxt88
  750. default "thunderxt88p1" if BR2_thunderxt88p1
  751. default "xgene1" if BR2_xgene1
  752. # armv8.1a
  753. default "thunderx2t99" if BR2_thunderx2t99
  754. default "thunderx2t99p1" if BR2_thunderx2t99p1
  755. default "vulcan" if BR2_vulcan
  756. # armv8.2a
  757. default "cortex-a55" if BR2_cortex_a55
  758. default "cortex-a75" if BR2_cortex_a75
  759. default "cortex-a75.cortex-a55" if BR2_cortex_a75_a55
  760. # armv8.3a
  761. default "saphira" if BR2_saphira
  762. config BR2_GCC_TARGET_ABI
  763. default "aapcs-linux" if BR2_arm || BR2_armeb
  764. default "lp64" if BR2_aarch64 || BR2_aarch64_be
  765. config BR2_GCC_TARGET_FPU
  766. default "vfp" if BR2_ARM_FPU_VFPV2
  767. default "vfpv3" if BR2_ARM_FPU_VFPV3
  768. default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
  769. default "vfpv4" if BR2_ARM_FPU_VFPV4
  770. default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
  771. default "neon" if BR2_ARM_FPU_NEON
  772. default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
  773. default "fpv4-sp-d16" if BR2_ARM_FPU_FPV4D16
  774. default "fpv5-sp-d16" if BR2_ARM_FPU_FPV5D16
  775. default "fpv5-d16" if BR2_ARM_FPU_FPV5DPD16
  776. default "fp-armv8" if BR2_ARM_FPU_FP_ARMV8
  777. default "neon-fp-armv8" if BR2_ARM_FPU_NEON_FP_ARMV8
  778. depends on BR2_arm || BR2_armeb
  779. config BR2_GCC_TARGET_FLOAT_ABI
  780. default "soft" if BR2_ARM_SOFT_FLOAT
  781. default "softfp" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABI
  782. default "hard" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABIHF
  783. config BR2_GCC_TARGET_MODE
  784. default "arm" if BR2_ARM_INSTRUCTIONS_ARM
  785. default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2
  786. config BR2_READELF_ARCH_NAME
  787. default "ARM" if BR2_arm || BR2_armeb
  788. default "AArch64" if BR2_aarch64 || BR2_aarch64_be
  789. # vim: ft=kconfig
  790. # -*- mode:kconfig; -*-