Config.in 12 KB

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  1. menu "Target options"
  2. config BR2_ARCH_IS_64
  3. bool
  4. config BR2_KERNEL_64_USERLAND_32
  5. bool
  6. config BR2_SOFT_FLOAT
  7. bool
  8. config BR2_ARCH_HAS_MMU_MANDATORY
  9. bool
  10. config BR2_ARCH_HAS_MMU_OPTIONAL
  11. bool
  12. choice
  13. prompt "Target Architecture"
  14. default BR2_i386
  15. help
  16. Select the target architecture family to build for.
  17. config BR2_arcle
  18. bool "ARC (little endian)"
  19. select BR2_ARCH_HAS_MMU_MANDATORY
  20. help
  21. Synopsys' DesignWare ARC Processor Cores are a family of
  22. 32-bit CPUs that can be used from deeply embedded to high
  23. performance host applications. Little endian.
  24. config BR2_arceb
  25. bool "ARC (big endian)"
  26. select BR2_ARCH_HAS_MMU_MANDATORY
  27. help
  28. Synopsys' DesignWare ARC Processor Cores are a family of
  29. 32-bit CPUs that can be used from deeply embedded to high
  30. performance host applications. Big endian.
  31. config BR2_arm
  32. bool "ARM (little endian)"
  33. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  34. help
  35. ARM is a 32-bit reduced instruction set computer (RISC)
  36. instruction set architecture (ISA) developed by ARM Holdings.
  37. Little endian.
  38. http://www.arm.com/
  39. http://en.wikipedia.org/wiki/ARM
  40. config BR2_armeb
  41. bool "ARM (big endian)"
  42. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  43. help
  44. ARM is a 32-bit reduced instruction set computer (RISC)
  45. instruction set architecture (ISA) developed by ARM Holdings.
  46. Big endian.
  47. http://www.arm.com/
  48. http://en.wikipedia.org/wiki/ARM
  49. config BR2_aarch64
  50. bool "AArch64 (little endian)"
  51. select BR2_ARCH_IS_64
  52. select BR2_ARCH_HAS_MMU_MANDATORY
  53. help
  54. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  55. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  56. http://en.wikipedia.org/wiki/ARM
  57. config BR2_aarch64_be
  58. bool "AArch64 (big endian)"
  59. select BR2_ARCH_IS_64
  60. select BR2_ARCH_HAS_MMU_MANDATORY
  61. help
  62. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  63. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  64. http://en.wikipedia.org/wiki/ARM
  65. config BR2_csky
  66. bool "csky"
  67. select BR2_ARCH_HAS_MMU_MANDATORY
  68. # Most variants are supported by gcc-9+, except one that is
  69. # handled as a special exception in package/gcc/Config.in.host
  70. select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
  71. help
  72. csky is processor IP from china.
  73. http://www.c-sky.com/
  74. http://www.github.com/c-sky
  75. config BR2_i386
  76. bool "i386"
  77. select BR2_ARCH_HAS_MMU_MANDATORY
  78. help
  79. Intel i386 architecture compatible microprocessor
  80. http://en.wikipedia.org/wiki/I386
  81. config BR2_m68k
  82. bool "m68k"
  83. # MMU support is set by the subarchitecture file, arch/Config.in.m68k
  84. help
  85. Motorola 68000 family microprocessor
  86. http://en.wikipedia.org/wiki/M68k
  87. config BR2_microblazeel
  88. bool "Microblaze AXI (little endian)"
  89. select BR2_ARCH_HAS_MMU_MANDATORY
  90. help
  91. Soft processor core designed for Xilinx FPGAs from Xilinx. AXI
  92. bus based architecture (little endian)
  93. http://www.xilinx.com
  94. http://en.wikipedia.org/wiki/Microblaze
  95. config BR2_microblazebe
  96. bool "Microblaze non-AXI (big endian)"
  97. select BR2_ARCH_HAS_MMU_MANDATORY
  98. help
  99. Soft processor core designed for Xilinx FPGAs from Xilinx. PLB
  100. bus based architecture (non-AXI, big endian)
  101. http://www.xilinx.com
  102. http://en.wikipedia.org/wiki/Microblaze
  103. config BR2_mips
  104. bool "MIPS (big endian)"
  105. select BR2_ARCH_HAS_MMU_MANDATORY
  106. help
  107. MIPS is a RISC microprocessor from MIPS Technologies. Big
  108. endian.
  109. http://www.mips.com/
  110. http://en.wikipedia.org/wiki/MIPS_Technologies
  111. config BR2_mipsel
  112. bool "MIPS (little endian)"
  113. select BR2_ARCH_HAS_MMU_MANDATORY
  114. help
  115. MIPS is a RISC microprocessor from MIPS Technologies. Little
  116. endian.
  117. http://www.mips.com/
  118. http://en.wikipedia.org/wiki/MIPS_Technologies
  119. config BR2_mips64
  120. bool "MIPS64 (big endian)"
  121. select BR2_ARCH_IS_64
  122. select BR2_ARCH_HAS_MMU_MANDATORY
  123. help
  124. MIPS is a RISC microprocessor from MIPS Technologies. Big
  125. endian.
  126. http://www.mips.com/
  127. http://en.wikipedia.org/wiki/MIPS_Technologies
  128. config BR2_mips64el
  129. bool "MIPS64 (little endian)"
  130. select BR2_ARCH_IS_64
  131. select BR2_ARCH_HAS_MMU_MANDATORY
  132. help
  133. MIPS is a RISC microprocessor from MIPS Technologies. Little
  134. endian.
  135. http://www.mips.com/
  136. http://en.wikipedia.org/wiki/MIPS_Technologies
  137. config BR2_nds32
  138. bool "nds32"
  139. select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  140. select BR2_ARCH_HAS_MMU_MANDATORY
  141. help
  142. nds32 is a 32-bit architecture developed by Andes Technology.
  143. https://en.wikipedia.org/wiki/Andes_Technology
  144. config BR2_nios2
  145. bool "Nios II"
  146. select BR2_ARCH_HAS_MMU_MANDATORY
  147. help
  148. Nios II is a soft core processor from Altera Corporation.
  149. http://www.altera.com/
  150. http://en.wikipedia.org/wiki/Nios_II
  151. config BR2_or1k
  152. bool "OpenRISC"
  153. select BR2_ARCH_HAS_MMU_MANDATORY
  154. help
  155. OpenRISC is a free and open processor for embedded system.
  156. http://openrisc.io
  157. config BR2_powerpc
  158. bool "PowerPC"
  159. select BR2_ARCH_HAS_MMU_MANDATORY
  160. help
  161. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  162. alliance. Big endian.
  163. http://www.power.org/
  164. http://en.wikipedia.org/wiki/Powerpc
  165. config BR2_powerpc64
  166. bool "PowerPC64 (big endian)"
  167. select BR2_ARCH_IS_64
  168. select BR2_ARCH_HAS_MMU_MANDATORY
  169. help
  170. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  171. alliance. Big endian.
  172. http://www.power.org/
  173. http://en.wikipedia.org/wiki/Powerpc
  174. config BR2_powerpc64le
  175. bool "PowerPC64 (little endian)"
  176. select BR2_ARCH_IS_64
  177. select BR2_ARCH_HAS_MMU_MANDATORY
  178. help
  179. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  180. alliance. Little endian.
  181. http://www.power.org/
  182. http://en.wikipedia.org/wiki/Powerpc
  183. config BR2_riscv
  184. bool "RISCV"
  185. select BR2_ARCH_HAS_MMU_MANDATORY
  186. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  187. help
  188. RISC-V is an open, free Instruction Set Architecture created
  189. by the UC Berkeley Architecture Research group and supported
  190. and promoted by RISC-V Foundation.
  191. https://riscv.org/
  192. https://en.wikipedia.org/wiki/RISC-V
  193. config BR2_sh
  194. bool "SuperH"
  195. select BR2_ARCH_HAS_MMU_OPTIONAL
  196. help
  197. SuperH (or SH) is a 32-bit reduced instruction set computer
  198. (RISC) instruction set architecture (ISA) developed by
  199. Hitachi.
  200. http://www.hitachi.com/
  201. http://en.wikipedia.org/wiki/SuperH
  202. config BR2_sparc
  203. bool "SPARC"
  204. select BR2_ARCH_HAS_MMU_MANDATORY
  205. help
  206. SPARC (from Scalable Processor Architecture) is a RISC
  207. instruction set architecture (ISA) developed by Sun
  208. Microsystems.
  209. http://www.oracle.com/sun
  210. http://en.wikipedia.org/wiki/Sparc
  211. config BR2_sparc64
  212. bool "SPARC64"
  213. select BR2_ARCH_IS_64
  214. select BR2_ARCH_HAS_MMU_MANDATORY
  215. help
  216. SPARC (from Scalable Processor Architecture) is a RISC
  217. instruction set architecture (ISA) developed by Sun
  218. Microsystems.
  219. http://www.oracle.com/sun
  220. http://en.wikipedia.org/wiki/Sparc
  221. config BR2_x86_64
  222. bool "x86_64"
  223. select BR2_ARCH_IS_64
  224. select BR2_ARCH_HAS_MMU_MANDATORY
  225. help
  226. x86-64 is an extension of the x86 instruction set (Intel i386
  227. architecture compatible microprocessor).
  228. http://en.wikipedia.org/wiki/X86_64
  229. config BR2_xtensa
  230. bool "Xtensa"
  231. # MMU support is set by the subarchitecture file, arch/Config.in.xtensa
  232. help
  233. Xtensa is a Tensilica processor IP architecture.
  234. http://en.wikipedia.org/wiki/Xtensa
  235. http://www.tensilica.com/
  236. endchoice
  237. # For some architectures or specific cores, our internal toolchain
  238. # backend is not suitable (like, missing support in upstream gcc, or
  239. # no ChipCo fork exists...)
  240. config BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  241. bool
  242. config BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT
  243. bool
  244. default y if !BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  245. # The following symbols are selected by the individual
  246. # Config.in.$ARCH files
  247. config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
  248. bool
  249. config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
  250. bool
  251. select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
  252. config BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  253. bool
  254. select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
  255. config BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  256. bool
  257. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  258. config BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  259. bool
  260. select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  261. config BR2_ARCH_NEEDS_GCC_AT_LEAST_8
  262. bool
  263. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  264. config BR2_ARCH_NEEDS_GCC_AT_LEAST_9
  265. bool
  266. select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
  267. # The following string values are defined by the individual
  268. # Config.in.$ARCH files
  269. config BR2_ARCH
  270. string
  271. config BR2_ENDIAN
  272. string
  273. config BR2_GCC_TARGET_ARCH
  274. string
  275. config BR2_GCC_TARGET_ABI
  276. string
  277. config BR2_GCC_TARGET_NAN
  278. string
  279. config BR2_GCC_TARGET_FP32_MODE
  280. string
  281. config BR2_GCC_TARGET_CPU
  282. string
  283. # The value of this option will be passed as --with-fpu=<value> when
  284. # building gcc (internal backend) or -mfpu=<value> in the toolchain
  285. # wrapper (external toolchain)
  286. config BR2_GCC_TARGET_FPU
  287. string
  288. # The value of this option will be passed as --with-float=<value> when
  289. # building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
  290. # wrapper (external toolchain)
  291. config BR2_GCC_TARGET_FLOAT_ABI
  292. string
  293. # The value of this option will be passed as --with-mode=<value> when
  294. # building gcc (internal backend) or -m<value> in the toolchain
  295. # wrapper (external toolchain)
  296. config BR2_GCC_TARGET_MODE
  297. string
  298. # Must be selected by binary formats that support shared libraries.
  299. config BR2_BINFMT_SUPPORTS_SHARED
  300. bool
  301. # Must match the name of the architecture from readelf point of view,
  302. # i.e the "Machine:" field of readelf output. See get_machine_name()
  303. # in binutils/readelf.c for the list of possible values.
  304. config BR2_READELF_ARCH_NAME
  305. string
  306. # Set up target binary format
  307. choice
  308. prompt "Target Binary Format"
  309. default BR2_BINFMT_ELF if BR2_USE_MMU
  310. default BR2_BINFMT_FLAT
  311. config BR2_BINFMT_ELF
  312. bool "ELF"
  313. depends on BR2_USE_MMU
  314. select BR2_BINFMT_SUPPORTS_SHARED
  315. help
  316. ELF (Executable and Linkable Format) is a format for libraries
  317. and executables used across different architectures and
  318. operating systems.
  319. config BR2_BINFMT_FLAT
  320. bool "FLAT"
  321. depends on !BR2_USE_MMU
  322. help
  323. FLAT binary is a relatively simple and lightweight executable
  324. format based on the original a.out format. It is widely used
  325. in environment where no MMU is available.
  326. endchoice
  327. # Set up flat binary type
  328. choice
  329. prompt "FLAT Binary type"
  330. default BR2_BINFMT_FLAT_ONE
  331. depends on BR2_BINFMT_FLAT
  332. config BR2_BINFMT_FLAT_ONE
  333. bool "One memory region"
  334. help
  335. All segments are linked into one memory region.
  336. config BR2_BINFMT_FLAT_SHARED
  337. bool "Shared binary"
  338. depends on BR2_m68k
  339. # Even though this really generates shared binaries, there is no libdl
  340. # and dlopen() cannot be used. So packages that require shared
  341. # libraries cannot be built. Therefore, we don't select
  342. # BR2_BINFMT_SUPPORTS_SHARED and therefore force BR2_STATIC_LIBS.
  343. # Although this adds -static to the compilation, that's not a problem
  344. # because the -mid-shared-library option overrides it.
  345. help
  346. Allow to load and link indiviual FLAT binaries at run time.
  347. endchoice
  348. if BR2_arcle || BR2_arceb
  349. source "arch/Config.in.arc"
  350. endif
  351. if BR2_arm || BR2_armeb || BR2_aarch64 || BR2_aarch64_be
  352. source "arch/Config.in.arm"
  353. endif
  354. if BR2_csky
  355. source "arch/Config.in.csky"
  356. endif
  357. if BR2_m68k
  358. source "arch/Config.in.m68k"
  359. endif
  360. if BR2_microblazeel || BR2_microblazebe
  361. source "arch/Config.in.microblaze"
  362. endif
  363. if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
  364. source "arch/Config.in.mips"
  365. endif
  366. if BR2_nds32
  367. source "arch/Config.in.nds32"
  368. endif
  369. if BR2_nios2
  370. source "arch/Config.in.nios2"
  371. endif
  372. if BR2_or1k
  373. source "arch/Config.in.or1k"
  374. endif
  375. if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
  376. source "arch/Config.in.powerpc"
  377. endif
  378. if BR2_riscv
  379. source "arch/Config.in.riscv"
  380. endif
  381. if BR2_sh
  382. source "arch/Config.in.sh"
  383. endif
  384. if BR2_sparc || BR2_sparc64
  385. source "arch/Config.in.sparc"
  386. endif
  387. if BR2_i386 || BR2_x86_64
  388. source "arch/Config.in.x86"
  389. endif
  390. if BR2_xtensa
  391. source "arch/Config.in.xtensa"
  392. endif
  393. endmenu # Target options