Config.in 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413
  1. menu "Target options"
  2. config BR2_ARCH_IS_64
  3. bool
  4. config BR2_KERNEL_64_USERLAND_32
  5. bool
  6. config BR2_SOFT_FLOAT
  7. bool
  8. config BR2_ARCH_HAS_MMU_MANDATORY
  9. bool
  10. config BR2_ARCH_HAS_MMU_OPTIONAL
  11. bool
  12. config BR2_ARCH_HAS_FDPIC_SUPPORT
  13. bool
  14. choice
  15. prompt "Target Architecture"
  16. default BR2_i386
  17. help
  18. Select the target architecture family to build for.
  19. config BR2_arcle
  20. bool "ARC (little endian)"
  21. select BR2_ARCH_HAS_MMU_MANDATORY
  22. help
  23. Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
  24. that can be used from deeply embedded to high performance host
  25. applications. Little endian.
  26. config BR2_arceb
  27. bool "ARC (big endian)"
  28. select BR2_ARCH_HAS_MMU_MANDATORY
  29. help
  30. Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
  31. that can be used from deeply embedded to high performance host
  32. applications. Big endian.
  33. config BR2_arm
  34. bool "ARM (little endian)"
  35. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  36. help
  37. ARM is a 32-bit reduced instruction set computer (RISC) instruction
  38. set architecture (ISA) developed by ARM Holdings. Little endian.
  39. http://www.arm.com/
  40. http://en.wikipedia.org/wiki/ARM
  41. config BR2_armeb
  42. bool "ARM (big endian)"
  43. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  44. help
  45. ARM is a 32-bit reduced instruction set computer (RISC) instruction
  46. set architecture (ISA) developed by ARM Holdings. Big endian.
  47. http://www.arm.com/
  48. http://en.wikipedia.org/wiki/ARM
  49. config BR2_aarch64
  50. bool "AArch64 (little endian)"
  51. select BR2_ARCH_IS_64
  52. select BR2_ARCH_HAS_MMU_MANDATORY
  53. help
  54. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  55. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  56. http://en.wikipedia.org/wiki/ARM
  57. config BR2_aarch64_be
  58. bool "AArch64 (big endian)"
  59. select BR2_ARCH_IS_64
  60. select BR2_ARCH_HAS_MMU_MANDATORY
  61. help
  62. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  63. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  64. http://en.wikipedia.org/wiki/ARM
  65. config BR2_bfin
  66. bool "Blackfin"
  67. select BR2_ARCH_HAS_FDPIC_SUPPORT
  68. help
  69. The Blackfin is a family of 16 or 32-bit microprocessors developed,
  70. manufactured and marketed by Analog Devices.
  71. http://www.analog.com/
  72. http://en.wikipedia.org/wiki/Blackfin
  73. config BR2_i386
  74. bool "i386"
  75. select BR2_ARCH_HAS_MMU_MANDATORY
  76. help
  77. Intel i386 architecture compatible microprocessor
  78. http://en.wikipedia.org/wiki/I386
  79. config BR2_m68k
  80. bool "m68k"
  81. select BR2_ARCH_HAS_MMU_MANDATORY
  82. depends on BROKEN # ice in uclibc / inet_ntoa_r
  83. help
  84. Motorola 68000 family microprocessor
  85. http://en.wikipedia.org/wiki/M68k
  86. config BR2_microblazeel
  87. bool "Microblaze AXI (little endian)"
  88. select BR2_ARCH_HAS_MMU_MANDATORY
  89. help
  90. Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus
  91. based architecture (little endian)
  92. http://www.xilinx.com
  93. http://en.wikipedia.org/wiki/Microblaze
  94. config BR2_microblazebe
  95. bool "Microblaze non-AXI (big endian)"
  96. select BR2_ARCH_HAS_MMU_MANDATORY
  97. help
  98. Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus
  99. based architecture (non-AXI, big endian)
  100. http://www.xilinx.com
  101. http://en.wikipedia.org/wiki/Microblaze
  102. config BR2_mips
  103. bool "MIPS (big endian)"
  104. select BR2_ARCH_HAS_MMU_MANDATORY
  105. help
  106. MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
  107. http://www.mips.com/
  108. http://en.wikipedia.org/wiki/MIPS_Technologies
  109. config BR2_mipsel
  110. bool "MIPS (little endian)"
  111. select BR2_ARCH_HAS_MMU_MANDATORY
  112. help
  113. MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
  114. http://www.mips.com/
  115. http://en.wikipedia.org/wiki/MIPS_Technologies
  116. config BR2_mips64
  117. bool "MIPS64 (big endian)"
  118. select BR2_ARCH_IS_64
  119. select BR2_ARCH_HAS_MMU_MANDATORY
  120. help
  121. MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
  122. http://www.mips.com/
  123. http://en.wikipedia.org/wiki/MIPS_Technologies
  124. config BR2_mips64el
  125. bool "MIPS64 (little endian)"
  126. select BR2_ARCH_IS_64
  127. select BR2_ARCH_HAS_MMU_MANDATORY
  128. help
  129. MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
  130. http://www.mips.com/
  131. http://en.wikipedia.org/wiki/MIPS_Technologies
  132. config BR2_nios2
  133. bool "Nios II"
  134. select BR2_ARCH_HAS_MMU_MANDATORY
  135. help
  136. Nios II is a soft core processor from Altera Corporation.
  137. http://www.altera.com/
  138. http://en.wikipedia.org/wiki/Nios_II
  139. config BR2_powerpc
  140. bool "PowerPC"
  141. select BR2_ARCH_HAS_MMU_MANDATORY
  142. help
  143. PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
  144. Big endian.
  145. http://www.power.org/
  146. http://en.wikipedia.org/wiki/Powerpc
  147. config BR2_powerpc64
  148. bool "PowerPC64 (big endian)"
  149. select BR2_ARCH_IS_64
  150. select BR2_ARCH_HAS_MMU_MANDATORY
  151. help
  152. PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
  153. Big endian.
  154. http://www.power.org/
  155. http://en.wikipedia.org/wiki/Powerpc
  156. config BR2_powerpc64le
  157. bool "PowerPC64 (little endian)"
  158. select BR2_ARCH_IS_64
  159. select BR2_ARCH_HAS_MMU_MANDATORY
  160. help
  161. PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
  162. Little endian.
  163. http://www.power.org/
  164. http://en.wikipedia.org/wiki/Powerpc
  165. config BR2_sh
  166. bool "SuperH"
  167. select BR2_ARCH_HAS_MMU_OPTIONAL
  168. help
  169. SuperH (or SH) is a 32-bit reduced instruction set computer (RISC)
  170. instruction set architecture (ISA) developed by Hitachi.
  171. http://www.hitachi.com/
  172. http://en.wikipedia.org/wiki/SuperH
  173. config BR2_sh64
  174. bool "SuperH64"
  175. depends on BR2_DEPRECATED_SINCE_2015_05
  176. select BR2_ARCH_HAS_MMU_MANDATORY
  177. help
  178. SuperH64 (or SH) is a 64-bit reduced instruction set computer (RISC)
  179. instruction set architecture (ISA) developed by Hitachi.
  180. http://www.hitachi.com/
  181. http://en.wikipedia.org/wiki/SuperH
  182. config BR2_sparc
  183. bool "SPARC"
  184. select BR2_ARCH_HAS_MMU_MANDATORY
  185. help
  186. SPARC (from Scalable Processor Architecture) is a RISC instruction
  187. set architecture (ISA) developed by Sun Microsystems.
  188. http://www.oracle.com/sun
  189. http://en.wikipedia.org/wiki/Sparc
  190. config BR2_sparc64
  191. bool "SPARC64"
  192. select BR2_ARCH_IS_64
  193. select BR2_ARCH_HAS_MMU_MANDATORY
  194. help
  195. SPARC (from Scalable Processor Architecture) is a RISC instruction
  196. set architecture (ISA) developed by Sun Microsystems.
  197. http://www.oracle.com/sun
  198. http://en.wikipedia.org/wiki/Sparc
  199. config BR2_x86_64
  200. bool "x86_64"
  201. select BR2_ARCH_IS_64
  202. select BR2_ARCH_HAS_MMU_MANDATORY
  203. help
  204. x86-64 is an extension of the x86 instruction set (Intel i386
  205. architecture compatible microprocessor).
  206. http://en.wikipedia.org/wiki/X86_64
  207. config BR2_xtensa
  208. bool "Xtensa"
  209. # MMU support is set by the subarchitecture file, arch/Config.in.xtensa
  210. help
  211. Xtensa is a Tensilica processor IP architecture.
  212. http://en.wikipedia.org/wiki/Xtensa
  213. http://www.tensilica.com/
  214. endchoice
  215. # The following string values are defined by the individual
  216. # Config.in.$ARCH files
  217. config BR2_ARCH
  218. string
  219. config BR2_ENDIAN
  220. string
  221. config BR2_GCC_TARGET_ARCH
  222. string
  223. config BR2_GCC_TARGET_ABI
  224. string
  225. config BR2_GCC_TARGET_CPU
  226. string
  227. config BR2_GCC_TARGET_CPU_REVISION
  228. string
  229. # The value of this option will be passed as --with-fpu=<value> when
  230. # building gcc (internal backend) or -mfpu=<value> in the toolchain
  231. # wrapper (external toolchain)
  232. config BR2_GCC_TARGET_FPU
  233. string
  234. # The value of this option will be passed as --with-float=<value> when
  235. # building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
  236. # wrapper (external toolchain)
  237. config BR2_GCC_TARGET_FLOAT_ABI
  238. string
  239. # The value of this option will be passed as --with-mode=<value> when
  240. # building gcc (internal backend) or -m<value> in the toolchain
  241. # wrapper (external toolchain)
  242. config BR2_GCC_TARGET_MODE
  243. string
  244. # If the architecture has atomic operations, select this:
  245. config BR2_ARCH_HAS_ATOMICS
  246. bool
  247. # Must be selected by binary formats that support shared libraries.
  248. config BR2_BINFMT_SUPPORTS_SHARED
  249. bool
  250. # Set up target binary format
  251. choice
  252. prompt "Target Binary Format"
  253. default BR2_BINFMT_ELF if BR2_USE_MMU
  254. default BR2_BINFMT_FDPIC if BR2_ARCH_HAS_FDPIC_SUPPORT
  255. default BR2_BINFMT_FLAT
  256. config BR2_BINFMT_ELF
  257. bool "ELF"
  258. depends on BR2_USE_MMU
  259. select BR2_BINFMT_SUPPORTS_SHARED
  260. help
  261. ELF (Executable and Linkable Format) is a format for libraries and
  262. executables used across different architectures and operating
  263. systems.
  264. config BR2_BINFMT_FDPIC
  265. bool "FDPIC"
  266. depends on BR2_ARCH_HAS_FDPIC_SUPPORT
  267. select BR2_BINFMT_SUPPORTS_SHARED
  268. help
  269. ELF FDPIC binaries are based on ELF, but allow the individual load
  270. segments of a binary to be located in memory independently of each
  271. other. This makes this format ideal for use in environments where no
  272. MMU is available.
  273. config BR2_BINFMT_FLAT
  274. bool "FLAT"
  275. depends on !BR2_USE_MMU
  276. help
  277. FLAT binary is a relatively simple and lightweight executable format
  278. based on the original a.out format. It is widely used in environment
  279. where no MMU is available.
  280. endchoice
  281. # Set up flat binary type
  282. choice
  283. prompt "FLAT Binary type"
  284. depends on BR2_BINFMT_FLAT
  285. default BR2_BINFMT_FLAT_ONE
  286. config BR2_BINFMT_FLAT_ONE
  287. bool "One memory region"
  288. help
  289. All segments are linked into one memory region.
  290. config BR2_BINFMT_FLAT_SEP_DATA
  291. bool "Separate data and code region"
  292. help
  293. Allow for the data and text segments to be separated and placed in
  294. different regions of memory.
  295. config BR2_BINFMT_FLAT_SHARED
  296. bool "Shared binary"
  297. # Even though this really generates shared binaries, there is no libdl
  298. # and dlopen() cannot be used. So packages that require shared
  299. # libraries cannot be built. Therefore, we don't select
  300. # BR2_BINFMT_SUPPORTS_SHARED and therefore force BR2_STATIC_LIBS.
  301. # Although this adds -static to the compilation, that's not a problem
  302. # because the -mid-shared-library option overrides it.
  303. help
  304. Allow to load and link indiviual FLAT binaries at run time.
  305. endchoice
  306. if BR2_arcle || BR2_arceb
  307. source "arch/Config.in.arc"
  308. endif
  309. if BR2_arm || BR2_armeb
  310. source "arch/Config.in.arm"
  311. endif
  312. if BR2_aarch64 || BR2_aarch64_be
  313. source "arch/Config.in.aarch64"
  314. endif
  315. if BR2_bfin
  316. source "arch/Config.in.bfin"
  317. endif
  318. if BR2_m68k
  319. source "arch/Config.in.m68k"
  320. endif
  321. if BR2_microblazeel || BR2_microblazebe
  322. source "arch/Config.in.microblaze"
  323. endif
  324. if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
  325. source "arch/Config.in.mips"
  326. endif
  327. if BR2_nios2
  328. source "arch/Config.in.nios2"
  329. endif
  330. if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
  331. source "arch/Config.in.powerpc"
  332. endif
  333. if BR2_sh || BR2_sh64
  334. source "arch/Config.in.sh"
  335. endif
  336. if BR2_sparc || BR2_sparc64
  337. source "arch/Config.in.sparc"
  338. endif
  339. if BR2_i386 || BR2_x86_64
  340. source "arch/Config.in.x86"
  341. endif
  342. if BR2_xtensa
  343. source "arch/Config.in.xtensa"
  344. endif
  345. endmenu # Target options