Config.in.arm 13 KB

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  1. # arm cpu features
  2. config BR2_ARM_CPU_HAS_NEON
  3. bool
  4. # for some cores, NEON support is optional
  5. config BR2_ARM_CPU_MAYBE_HAS_NEON
  6. bool
  7. # for some cores, VFPv2 is optional
  8. config BR2_ARM_CPU_MAYBE_HAS_VFPV2
  9. bool
  10. config BR2_ARM_CPU_HAS_VFPV2
  11. bool
  12. # for some cores, VFPv3 is optional
  13. config BR2_ARM_CPU_MAYBE_HAS_VFPV3
  14. bool
  15. select BR2_ARM_CPU_MAYBE_HAS_VFPV2
  16. config BR2_ARM_CPU_HAS_VFPV3
  17. bool
  18. select BR2_ARM_CPU_HAS_VFPV2
  19. # for some cores, VFPv4 is optional
  20. config BR2_ARM_CPU_MAYBE_HAS_VFPV4
  21. bool
  22. select BR2_ARM_CPU_MAYBE_HAS_VFPV3
  23. config BR2_ARM_CPU_HAS_VFPV4
  24. bool
  25. select BR2_ARM_CPU_HAS_VFPV3
  26. config BR2_ARM_CPU_HAS_ARM
  27. bool
  28. config BR2_ARM_CPU_HAS_THUMB
  29. bool
  30. config BR2_ARM_CPU_HAS_THUMB2
  31. bool
  32. config BR2_ARM_CPU_ARMV4
  33. bool
  34. config BR2_ARM_CPU_ARMV5
  35. bool
  36. config BR2_ARM_CPU_ARMV6
  37. bool
  38. config BR2_ARM_CPU_ARMV7A
  39. bool
  40. choice
  41. prompt "Target Architecture Variant"
  42. depends on BR2_arm || BR2_armeb
  43. default BR2_arm926t
  44. help
  45. Specific CPU variant to use
  46. config BR2_arm920t
  47. bool "arm920t"
  48. select BR2_ARM_CPU_HAS_ARM
  49. select BR2_ARM_CPU_HAS_THUMB
  50. select BR2_ARM_CPU_ARMV4
  51. select BR2_ARCH_HAS_MMU_OPTIONAL
  52. config BR2_arm922t
  53. bool "arm922t"
  54. select BR2_ARM_CPU_HAS_ARM
  55. select BR2_ARM_CPU_HAS_THUMB
  56. select BR2_ARM_CPU_ARMV4
  57. select BR2_ARCH_HAS_MMU_OPTIONAL
  58. config BR2_arm926t
  59. bool "arm926t"
  60. select BR2_ARM_CPU_HAS_ARM
  61. select BR2_ARM_CPU_MAYBE_HAS_VFPV2
  62. select BR2_ARM_CPU_HAS_THUMB
  63. select BR2_ARM_CPU_ARMV5
  64. select BR2_ARCH_HAS_MMU_OPTIONAL
  65. config BR2_arm1136j_s
  66. bool "arm1136j-s"
  67. select BR2_ARM_CPU_HAS_ARM
  68. select BR2_ARM_CPU_HAS_THUMB
  69. select BR2_ARM_CPU_ARMV6
  70. select BR2_ARCH_HAS_MMU_OPTIONAL
  71. config BR2_arm1136jf_s
  72. bool "arm1136jf-s"
  73. select BR2_ARM_CPU_HAS_ARM
  74. select BR2_ARM_CPU_HAS_VFPV2
  75. select BR2_ARM_CPU_HAS_THUMB
  76. select BR2_ARM_CPU_ARMV6
  77. select BR2_ARCH_HAS_MMU_OPTIONAL
  78. config BR2_arm1176jz_s
  79. bool "arm1176jz-s"
  80. select BR2_ARM_CPU_HAS_ARM
  81. select BR2_ARM_CPU_HAS_THUMB
  82. select BR2_ARM_CPU_ARMV6
  83. select BR2_ARCH_HAS_MMU_OPTIONAL
  84. config BR2_arm1176jzf_s
  85. bool "arm1176jzf-s"
  86. select BR2_ARM_CPU_HAS_ARM
  87. select BR2_ARM_CPU_HAS_VFPV2
  88. select BR2_ARM_CPU_HAS_THUMB
  89. select BR2_ARM_CPU_ARMV6
  90. select BR2_ARCH_HAS_MMU_OPTIONAL
  91. config BR2_cortex_a5
  92. bool "cortex-A5"
  93. select BR2_ARM_CPU_HAS_ARM
  94. select BR2_ARM_CPU_MAYBE_HAS_NEON
  95. select BR2_ARM_CPU_MAYBE_HAS_VFPV4
  96. select BR2_ARM_CPU_HAS_THUMB2
  97. select BR2_ARM_CPU_ARMV7A
  98. select BR2_ARCH_HAS_MMU_OPTIONAL
  99. config BR2_cortex_a7
  100. bool "cortex-A7"
  101. select BR2_ARM_CPU_HAS_ARM
  102. select BR2_ARM_CPU_HAS_NEON
  103. select BR2_ARM_CPU_HAS_VFPV4
  104. select BR2_ARM_CPU_HAS_THUMB2
  105. select BR2_ARM_CPU_ARMV7A
  106. select BR2_ARCH_HAS_MMU_OPTIONAL
  107. config BR2_cortex_a8
  108. bool "cortex-A8"
  109. select BR2_ARM_CPU_HAS_ARM
  110. select BR2_ARM_CPU_HAS_NEON
  111. select BR2_ARM_CPU_HAS_VFPV3
  112. select BR2_ARM_CPU_HAS_THUMB2
  113. select BR2_ARM_CPU_ARMV7A
  114. select BR2_ARCH_HAS_MMU_OPTIONAL
  115. config BR2_cortex_a9
  116. bool "cortex-A9"
  117. select BR2_ARM_CPU_HAS_ARM
  118. select BR2_ARM_CPU_MAYBE_HAS_NEON
  119. select BR2_ARM_CPU_MAYBE_HAS_VFPV3
  120. select BR2_ARM_CPU_HAS_THUMB2
  121. select BR2_ARM_CPU_ARMV7A
  122. select BR2_ARCH_HAS_MMU_OPTIONAL
  123. config BR2_cortex_a12
  124. bool "cortex-A12"
  125. select BR2_ARM_CPU_HAS_ARM
  126. select BR2_ARM_CPU_HAS_NEON
  127. select BR2_ARM_CPU_HAS_VFPV4
  128. select BR2_ARM_CPU_HAS_THUMB2
  129. select BR2_ARM_CPU_ARMV7A
  130. select BR2_ARCH_HAS_MMU_OPTIONAL
  131. config BR2_cortex_a15
  132. bool "cortex-A15"
  133. select BR2_ARM_CPU_HAS_ARM
  134. select BR2_ARM_CPU_HAS_NEON
  135. select BR2_ARM_CPU_HAS_VFPV4
  136. select BR2_ARM_CPU_HAS_THUMB2
  137. select BR2_ARM_CPU_ARMV7A
  138. select BR2_ARCH_HAS_MMU_OPTIONAL
  139. config BR2_cortex_m3
  140. bool "cortex-M3"
  141. select BR2_ARM_CPU_HAS_THUMB
  142. select BR2_ARM_CPU_HAS_THUMB2
  143. config BR2_fa526
  144. bool "fa526/626"
  145. select BR2_ARM_CPU_HAS_ARM
  146. select BR2_ARM_CPU_ARMV4
  147. select BR2_ARCH_HAS_MMU_OPTIONAL
  148. config BR2_pj4
  149. bool "pj4"
  150. select BR2_ARM_CPU_HAS_ARM
  151. select BR2_ARM_CPU_HAS_VFPV3
  152. select BR2_ARM_CPU_ARMV7A
  153. select BR2_ARCH_HAS_MMU_OPTIONAL
  154. config BR2_strongarm
  155. bool "strongarm sa110/sa1100"
  156. select BR2_ARM_CPU_HAS_ARM
  157. select BR2_ARM_CPU_ARMV4
  158. select BR2_ARCH_HAS_MMU_OPTIONAL
  159. config BR2_xscale
  160. bool "xscale"
  161. select BR2_ARM_CPU_HAS_ARM
  162. select BR2_ARM_CPU_HAS_THUMB
  163. select BR2_ARM_CPU_ARMV5
  164. select BR2_ARCH_HAS_MMU_OPTIONAL
  165. config BR2_iwmmxt
  166. bool "iwmmxt"
  167. select BR2_ARM_CPU_HAS_ARM
  168. select BR2_ARM_CPU_ARMV5
  169. select BR2_ARCH_HAS_MMU_OPTIONAL
  170. endchoice
  171. choice
  172. prompt "Target ABI"
  173. depends on BR2_arm || BR2_armeb
  174. default BR2_ARM_EABI
  175. help
  176. Application Binary Interface to use. The Application Binary
  177. Interface describes the calling conventions (how arguments
  178. are passed to functions, how the return value is passed, how
  179. system calls are made, etc.).
  180. config BR2_ARM_EABI
  181. bool "EABI"
  182. help
  183. The EABI is currently the standard ARM ABI, which is used in
  184. most projects. It supports both the 'soft' floating point
  185. model (in which floating point instructions are emulated in
  186. software) and the 'softfp' floating point model (in which
  187. floating point instructions are executed using an hardware
  188. floating point unit, but floating point arguments to
  189. functions are passed in integer registers).
  190. The 'softfp' floating point model is link-compatible with
  191. the 'soft' floating point model, i.e you can link a library
  192. built 'soft' with some other code built 'softfp'.
  193. However, passing the floating point arguments in integer
  194. registers is a bit inefficient, so if your ARM processor has
  195. a floating point unit, and you don't have pre-compiled
  196. 'soft' or 'softfp' code, using the EABIhf ABI will provide
  197. better floating point performances.
  198. If your processor does not have a floating point unit, then
  199. you must use this ABI.
  200. config BR2_ARM_EABIHF
  201. bool "EABIhf"
  202. depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2 || BR2_ARM_CPU_HAS_VFPV2
  203. help
  204. The EABIhf is an extension of EABI which supports the 'hard'
  205. floating point model. This model uses the floating point
  206. unit to execute floating point instructions, and passes
  207. floating point arguments in floating point registers.
  208. It is more efficient than EABI for floating point related
  209. workload. However, it does not allow to link against code
  210. that has been pre-built for the 'soft' or 'softfp' floating
  211. point models.
  212. If your processor has a floating point unit, and you don't
  213. depend on existing pre-compiled code, this option is most
  214. likely the best choice.
  215. endchoice
  216. config BR2_ARM_ENABLE_NEON
  217. bool "Enable NEON SIMD extension support"
  218. depends on BR2_ARM_CPU_MAYBE_HAS_NEON
  219. select BR2_ARM_CPU_HAS_NEON
  220. help
  221. For some CPU cores, the NEON SIMD extension is optional.
  222. Select this option if you are certain your particular
  223. implementation has NEON support and you want to use it.
  224. choice
  225. prompt "Floating point strategy"
  226. depends on BR2_ARM_EABI || BR2_ARM_EABIHF
  227. default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
  228. default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
  229. default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
  230. default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_VFPV2
  231. config BR2_ARM_SOFT_FLOAT
  232. bool "Soft float"
  233. depends on BR2_ARM_EABI
  234. select BR2_SOFT_FLOAT
  235. help
  236. This option allows to use software emulated floating
  237. point. It should be used for ARM cores that do not include a
  238. Vector Floating Point unit, such as ARMv5 cores (ARM926 for
  239. example) or certain ARMv6 cores.
  240. config BR2_ARM_FPU_VFPV2
  241. bool "VFPv2"
  242. depends on BR2_ARM_CPU_HAS_VFPV2 || BR2_ARM_CPU_MAYBE_HAS_VFPV2
  243. help
  244. This option allows to use the VFPv2 floating point unit, as
  245. available in some ARMv5 processors (ARM926EJ-S) and some
  246. ARMv6 processors (ARM1136JF-S, ARM1176JZF-S and ARM11
  247. MPCore).
  248. Note that this option is also safe to use for newer cores
  249. such as Cortex-A, because the VFPv3 and VFPv4 units are
  250. backward compatible with VFPv2.
  251. config BR2_ARM_FPU_VFPV3
  252. bool "VFPv3"
  253. depends on BR2_ARM_CPU_HAS_VFPV3 || BR2_ARM_CPU_MAYBE_HAS_VFPV3
  254. help
  255. This option allows to use the VFPv3 floating point unit, as
  256. available in some ARMv7 processors (Cortex-A{8, 9}). This
  257. option requires a VFPv3 unit that has 32 double-precision
  258. registers, which is not necessarily the case in all SOCs
  259. based on Cortex-A{8, 9}. If you're unsure, use VFPv3-D16
  260. instead, which is guaranteed to work on all Cortex-A{8, 9}.
  261. Note that this option is also safe to use for newer cores
  262. that have a VFPv4 unit, because VFPv4 is backward compatible
  263. with VFPv3. They must of course also have 32
  264. double-precision registers.
  265. config BR2_ARM_FPU_VFPV3D16
  266. bool "VFPv3-D16"
  267. depends on BR2_ARM_CPU_HAS_VFPV3 || BR2_ARM_CPU_MAYBE_HAS_VFPV3
  268. help
  269. This option allows to use the VFPv3 floating point unit, as
  270. available in some ARMv7 processors (Cortex-A{8, 9}). This
  271. option requires a VFPv3 unit that has 16 double-precision
  272. registers, which is generally the case in all SOCs based on
  273. Cortex-A{8, 9}, even though VFPv3 is technically optional on
  274. Cortex-A9. This is the safest option for those cores.
  275. Note that this option is also safe to use for newer cores
  276. such that have a VFPv4 unit, because the VFPv4 is backward
  277. compatible with VFPv3.
  278. config BR2_ARM_FPU_VFPV4
  279. bool "VFPv4"
  280. depends on BR2_ARM_CPU_HAS_VFPV4 || BR2_ARM_CPU_MAYBE_HAS_VFPV4
  281. help
  282. This option allows to use the VFPv4 floating point unit, as
  283. available in some ARMv7 processors (Cortex-A{5, 7, 12,
  284. 15}). This option requires a VFPv4 unit that has 32
  285. double-precision registers, which is not necessarily the
  286. case in all SOCs based on Cortex-A{5, 7, 12, 15}. If you're
  287. unsure, you should probably use VFPv4-D16 instead.
  288. Note that if you want binary code that works on all ARMv7
  289. cores, including the earlier Cortex-A{8, 9}, you should
  290. instead select VFPv3.
  291. config BR2_ARM_FPU_VFPV4D16
  292. bool "VFPv4-D16"
  293. depends on BR2_ARM_CPU_HAS_VFPV4 || BR2_ARM_CPU_MAYBE_HAS_VFPV4
  294. help
  295. This option allows to use the VFPv4 floating point unit, as
  296. available in some ARMv7 processors (Cortex-A{5, 7, 12,
  297. 15}). This option requires a VFPv4 unit that has 16
  298. double-precision registers, which is always available on
  299. Cortex-A12 and Cortex-A15, but optional on Cortex-A5 and
  300. Cortex-A7.
  301. Note that if you want binary code that works on all ARMv7
  302. cores, including the earlier Cortex-A{8, 9}, you should
  303. instead select VFPv3-D16.
  304. config BR2_ARM_FPU_NEON
  305. bool "NEON"
  306. depends on BR2_ARM_CPU_HAS_NEON
  307. help
  308. This option allows to use the NEON SIMD unit, as available
  309. in some ARMv7 processors, as a floating-point unit. It
  310. should however be noted that using NEON for floating point
  311. operations doesn't provide a complete compatibility with the
  312. IEEE 754.
  313. config BR2_ARM_FPU_NEON_VFPV4
  314. bool "NEON/VFPv4"
  315. depends on BR2_ARM_CPU_HAS_VFPV4 || BR2_ARM_CPU_MAYBE_HAS_VFPV4
  316. depends on BR2_ARM_CPU_HAS_NEON
  317. help
  318. This option allows to use both the VFPv4 and the NEON SIMD
  319. units for floating point operations. Note that some ARMv7
  320. cores do not necessarily have VFPv4 and/or NEON support, for
  321. example on Cortex-A5 and Cortex-A7, support for VFPv4 and
  322. NEON is optional.
  323. endchoice
  324. choice
  325. prompt "ARM instruction set"
  326. config BR2_ARM_INSTRUCTIONS_ARM
  327. bool "ARM"
  328. depends on BR2_ARM_CPU_HAS_ARM
  329. help
  330. This option instructs the compiler to generate regular ARM
  331. instructions, that are all 32 bits wide.
  332. config BR2_ARM_INSTRUCTIONS_THUMB
  333. bool "Thumb"
  334. depends on BR2_ARM_CPU_HAS_THUMB
  335. help
  336. This option instructions the compiler to generate Thumb
  337. instructions, which allows to mix 16 bits instructions and
  338. 32 bits instructions. This generally provides a much smaller
  339. compiled binary size.
  340. config BR2_ARM_INSTRUCTIONS_THUMB2
  341. bool "Thumb2"
  342. depends on BR2_ARM_CPU_HAS_THUMB2
  343. help
  344. This option instructions the compiler to generate Thumb2
  345. instructions, which allows to mix 16 bits instructions and
  346. 32 bits instructions. This generally provides a much smaller
  347. compiled binary size.
  348. endchoice
  349. config BR2_ARCH
  350. default "arm" if BR2_arm
  351. default "armeb" if BR2_armeb
  352. config BR2_ENDIAN
  353. default "LITTLE" if BR2_arm
  354. default "BIG" if BR2_armeb
  355. config BR2_ARCH_HAS_ATOMICS
  356. default y
  357. config BR2_GCC_TARGET_CPU
  358. default "arm920t" if BR2_arm920t
  359. default "arm922t" if BR2_arm922t
  360. default "arm926ej-s" if BR2_arm926t
  361. default "arm1136j-s" if BR2_arm1136j_s
  362. default "arm1136jf-s" if BR2_arm1136jf_s
  363. default "arm1176jz-s" if BR2_arm1176jz_s
  364. default "arm1176jzf-s" if BR2_arm1176jzf_s
  365. default "cortex-a5" if BR2_cortex_a5
  366. default "cortex-a7" if BR2_cortex_a7
  367. default "cortex-a8" if BR2_cortex_a8
  368. default "cortex-a9" if BR2_cortex_a9
  369. default "cortex-a12" if BR2_cortex_a12
  370. default "cortex-a15" if BR2_cortex_a15
  371. default "cortex-m3" if BR2_cortex_m3
  372. default "fa526" if BR2_fa526
  373. default "marvell-pj4" if BR2_pj4
  374. default "strongarm" if BR2_strongarm
  375. default "xscale" if BR2_xscale
  376. default "iwmmxt" if BR2_iwmmxt
  377. config BR2_GCC_TARGET_ABI
  378. default "aapcs-linux"
  379. config BR2_GCC_TARGET_FPU
  380. default "vfp" if BR2_ARM_FPU_VFPV2
  381. default "vfpv3" if BR2_ARM_FPU_VFPV3
  382. default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
  383. default "vfpv4" if BR2_ARM_FPU_VFPV4
  384. default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
  385. default "neon" if BR2_ARM_FPU_NEON
  386. default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
  387. config BR2_GCC_TARGET_FLOAT_ABI
  388. default "soft" if BR2_ARM_SOFT_FLOAT
  389. default "softfp" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABI
  390. default "hard" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABIHF
  391. config BR2_GCC_TARGET_MODE
  392. default "arm" if BR2_ARM_INSTRUCTIONS_ARM
  393. default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2