0001-mips-Do-not-include-hi-and-lo-in-clobber-list-for-R6.patch 4.6 KB

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  1. From bb04c220d82598066eeadf49defaec1157d4d206 Mon Sep 17 00:00:00 2001
  2. From: Romain Naour <romain.naour@gmail.com>
  3. Date: Sat, 25 Jul 2020 11:46:01 +0200
  4. Subject: [PATCH] mips: Do not include hi and lo in clobber list for R6
  5. MIME-Version: 1.0
  6. Content-Type: text/plain; charset=UTF-8
  7. Content-Transfer-Encoding: 8bit
  8. From [1]
  9. "GCC 10 (PR 91233) won't silently allow registers that are not architecturally
  10. available to be present in the clobber list anymore, resulting in build failure
  11. for mips*r6 targets in form of:
  12. ...
  13. .../sysdep.h:146:2: error: the register ‘lo’ cannot be clobbered in ‘asm’ for the current target
  14. 146 | __asm__ volatile ( \
  15. | ^~~~~~~
  16. This is because base R6 ISA doesn't define hi and lo registers w/o DSP extension.
  17. This patch provides the alternative clobber list for r6 targets that won't include
  18. those registers."
  19. Since kernel 5.4 and mips support for generic vDSO [2], the kernel fail to build
  20. for mips r6 cpus with gcc 10 for the same reason as glibc.
  21. [1] https://sourceware.org/git/?p=glibc.git;a=commit;h=020b2a97bb15f807c0482f0faee2184ed05bcad8
  22. [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=24640f233b466051ad3a5d2786d2951e43026c9d
  23. Signed-off-by: Romain Naour <romain.naour@gmail.com>
  24. ---
  25. arch/mips/include/asm/vdso/gettimeofday.h | 45 +++++++++++++++++++++++
  26. 1 file changed, 45 insertions(+)
  27. diff --git a/arch/mips/include/asm/vdso/gettimeofday.h b/arch/mips/include/asm/vdso/gettimeofday.h
  28. index 0ae9b4cbc153..ea600e0ebfe7 100644
  29. --- a/arch/mips/include/asm/vdso/gettimeofday.h
  30. +++ b/arch/mips/include/asm/vdso/gettimeofday.h
  31. @@ -36,12 +36,21 @@ static __always_inline long gettimeofday_fallback(
  32. register long nr asm("v0") = __NR_gettimeofday;
  33. register long error asm("a3");
  34. +#if MIPS_ISA_REV >= 6
  35. + asm volatile(
  36. + " syscall\n"
  37. + : "=r" (ret), "=r" (error)
  38. + : "r" (tv), "r" (tz), "r" (nr)
  39. + : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
  40. + "$14", "$15", "$24", "$25", "memory");
  41. +#else
  42. asm volatile(
  43. " syscall\n"
  44. : "=r" (ret), "=r" (error)
  45. : "r" (tv), "r" (tz), "r" (nr)
  46. : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
  47. "$14", "$15", "$24", "$25", "hi", "lo", "memory");
  48. +#endif
  49. return error ? -ret : ret;
  50. }
  51. @@ -60,12 +69,21 @@ static __always_inline long clock_gettime_fallback(
  52. #endif
  53. register long error asm("a3");
  54. +#if MIPS_ISA_REV >= 6
  55. + asm volatile(
  56. + " syscall\n"
  57. + : "=r" (ret), "=r" (error)
  58. + : "r" (clkid), "r" (ts), "r" (nr)
  59. + : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
  60. + "$14", "$15", "$24", "$25", "memory");
  61. +#else
  62. asm volatile(
  63. " syscall\n"
  64. : "=r" (ret), "=r" (error)
  65. : "r" (clkid), "r" (ts), "r" (nr)
  66. : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
  67. "$14", "$15", "$24", "$25", "hi", "lo", "memory");
  68. +#endif
  69. return error ? -ret : ret;
  70. }
  71. @@ -84,12 +102,21 @@ static __always_inline int clock_getres_fallback(
  72. #endif
  73. register long error asm("a3");
  74. +#if MIPS_ISA_REV >= 6
  75. + asm volatile(
  76. + " syscall\n"
  77. + : "=r" (ret), "=r" (error)
  78. + : "r" (clkid), "r" (ts), "r" (nr)
  79. + : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
  80. + "$14", "$15", "$24", "$25", "memory");
  81. +#else
  82. asm volatile(
  83. " syscall\n"
  84. : "=r" (ret), "=r" (error)
  85. : "r" (clkid), "r" (ts), "r" (nr)
  86. : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
  87. "$14", "$15", "$24", "$25", "hi", "lo", "memory");
  88. +#endif
  89. return error ? -ret : ret;
  90. }
  91. @@ -108,12 +135,21 @@ static __always_inline long clock_gettime32_fallback(
  92. register long nr asm("v0") = __NR_clock_gettime;
  93. register long error asm("a3");
  94. +#if MIPS_ISA_REV >= 6
  95. + asm volatile(
  96. + " syscall\n"
  97. + : "=r" (ret), "=r" (error)
  98. + : "r" (clkid), "r" (ts), "r" (nr)
  99. + : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
  100. + "$14", "$15", "$24", "$25", "memory");
  101. +#else
  102. asm volatile(
  103. " syscall\n"
  104. : "=r" (ret), "=r" (error)
  105. : "r" (clkid), "r" (ts), "r" (nr)
  106. : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
  107. "$14", "$15", "$24", "$25", "hi", "lo", "memory");
  108. +#endif
  109. return error ? -ret : ret;
  110. }
  111. @@ -128,12 +164,21 @@ static __always_inline int clock_getres32_fallback(
  112. register long nr asm("v0") = __NR_clock_getres;
  113. register long error asm("a3");
  114. +#if MIPS_ISA_REV >= 6
  115. + asm volatile(
  116. + " syscall\n"
  117. + : "=r" (ret), "=r" (error)
  118. + : "r" (clkid), "r" (ts), "r" (nr)
  119. + : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
  120. + "$14", "$15", "$24", "$25", "memory");
  121. +#else
  122. asm volatile(
  123. " syscall\n"
  124. : "=r" (ret), "=r" (error)
  125. : "r" (clkid), "r" (ts), "r" (nr)
  126. : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
  127. "$14", "$15", "$24", "$25", "hi", "lo", "memory");
  128. +#endif
  129. return error ? -ret : ret;
  130. }
  131. --
  132. 2.25.4